Table of Contents

1. Rapid design exploration using Vitis Model Composer
2. How to access the examples and quick guides?
3. Videos
4. AI Engine Examples
5. HLS Examples
6. Quick Guides
7. What is new?

Rapid design exploration using Vitis Model Composer

Vitis Model Composer provides a library of performance-optimized blocks for design and implementation of DSP algorithms on Xilinx devices. The Vitis Model Composer AI Engine, HLS and HDL libraries within the Simulink environment, enable the rapid design exploration of an algorithm and accelerates the path to production.

How to access the examples and quick guides?

We are storing and managing a subset of the Vitis Model Composer examples (AI Engine and HLS Library) in GitHub. This way, users will have access to the most up-to-date examples. You can get the examples from GitHub or preferably directly from Vitis Model Composer.

Click here to learn how to access Vitis Model Composer examples.

Videos

Design for Versal AI Engines (20 minutes)

AI Engine Examples

General Examples

Topic	Description
Importing Kernels and Graphs into Model Composer	Examples on importing Kernels and Graphs into Model Composer as blocks. This include importing templatized class based kernels, templatized AI Engine functions, and graphs.
Run time parameters (RTP)	Examples of kernels with RTP input. RTP inputs can be sync or async.
DSP Functions	AI Engine FIR filters and FFT. Importing Matrix Multiply as a graph into Vitis Model Composer.
Designs with both AI Engine and HDL blocks	Examples of designs with both AI Engine kernels and HDL blocks. Here you can see examples of importing Verliog code into Model Composer and co-simulation with AI Engine blocks at high speeds.
Design with both AI Engines and HLS kernels	Example of a design with both AI Engine kernels and an HLS kernel.

Design Examples

Topic	Description
Super Sample Rate FIR filter	This design showcases a Super Sample Rate FIR filter to process a 4GSPS input stream. In this design we also compare the output of our AI Engine subsystem with the output of a Simulink FIR block (our golden reference) both in time and in frequency.
Super Sample Rate FIR filter with PL	This design showcases a Super Sample Rate FIR filter to process a 4GSPS input stream. In this design we consider latencies within the kernels, which are implemented into the FIFO's included in AXI-Stream Interconnect(PL).
Dual Stream Super Sample Rate FIR filter	This design showcases a Dual Stream Super Sample Rate FIR filter to process a 16GSPS input stream. In this design we also compare the output of the AI Engine subsystem with the output of a Simulink FIR block (the golden reference).
2D FFT (AI Engines + HDL/HLS)	The designs here showcase 2D-FFTs that are implemented both in AI Engines and Programmable Logic(PL). In one example the PL is implemented using HLS and in another example the PL is implemented using HDL blocks in Vitis Model Composer.
TX Chain 200MHz	This design showcases the Vitis Model Composer implementation of the commslib example, TX chain 200MHz, which is part of the communications Library Early access program.
Pseudo Inverse 64x32	This design showcases an AI Engine implementation of a 64x32 Pseudo Inverse in Vitis Model Composer. The AI Engine output is compared with the output of the pseudo inverse block in Simulink which is used as a reference.

HLS Examples

Topic	Description
Color Detection	This example demonstrates color detection on an input video.
Importing FIR Filter into Model Composer	This example demonstrates a 103 tap symmetric FIR filter
Import Function feature examples	This is a set of simple examples to demonstrate importing C/C++ functions into Model Composer as a blocks.
Optical Flow	This example demonstrates an implementation of dense optical flow in Model Composer.
Sobel Edge Detection	This example demonestrates an implemntation of sobel edge detection algorithm in Model Composer
Video Frame Rotation	This example demonstrates rotating video frames by a certain angle in Model Composer.

Quick Guides

Topic	Description
What are Variable-Size Signals?	All you need to know about Variable-Size Signals in Simulink.
How to properly set the Signal Size property on AI Engine kernel blocks with stream or cascade outputs?	Setting the signal size property for AI Engine kernels with stream and cascade outputs.
Connecting AI Engine blocks with HDL blocks	Setting the properties of the AIE to HDL and HDL to AIE blocks can be tricky. This tutorial explains how to set these parameters.

What's new in 2021.2?

AI Engines

• With a click of a button, run a design with AI Engines and PL (HLS, HDL) blocks into a Versal AI Core hardware.
• Significant speed up in Simulink simulation by parallel compilation of AIE blocks.
• Enhancements to AI Engine constraint editor
• Addition of DDS and Mixer blocks in the AIE DSP library.
• Enhancements to "to fixed size" and "to variable size" blocks.
• Support of int64 and uint64 data types.
• Support for accfloat and caccfloat
• Enhancement to GitHub examples and incorporation of HLS examples in GitHub
• Generated data flow graph code now includes PLIO specification
• Enhanced usability to download and browse examples from GitHub.
• Support for AIE source blocks.
• xmcVitisRead and xmcVitisWrite utilities to read/write data files for AIE Simulator and/or x86Simulator
• Systematize GUI parameters of AIE dsplib blocks
• New 64x32 Pseudo Inverse design example.
• New Dual-Stream SSR Filter example with 64 AI Engine kernels and upto 16 GSPS throughput.

HDL

• Support of Asymmetric read/write data widths for FIFO block

HLS

• Supports simulation and implementation of HLS based C code that utilizes the Xilinx FIR, FFT, DDS Logicores

General

• MATLAB Support - R2020a, R2020b, and R2021a
• Newly added support for Ubuntu 20.04

---

Copyright 2021 Xilinx

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.