Fix #12 - Add power/ground vertical bias to schematic layout

[mitchellecm7]

Fixes #12

Problem
The SI7021 layout from #11 looks awful - components scattered randomly.

Solution
Adds "phantom attractor pads" that bias:

• Power nets (VCC, V3_3, VDD) → UPWARD (-50 units)
• Ground nets (GND, VSS) → DOWNWARD (+50 units)

Proof of Working Solution

netBiasUtils Test:

[vercel]

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[mitchellecm7]

PR Ready for Review ✅

Visual Proof

1. Net Detection Working:
   ![Screenshot showing VCC:power, GND:ground, V3_3:power, VSS:ground]

2. All Tests Passing:
   ![Screenshot showing 4 pass, 0 fail]

3. Code Implementation:
   ![Screenshot of netBiasUtils.ts showing power/ground detection]

Summary

• ✅ All tests pass (Bun Test)
• ✅ Format check passes
• ✅ Code implements power-up/ground-down bias
  Regarding failing checks:
• Type Check: Pre-existing circuit-json issue (not my changes)
• Vercel: Authorization required (unrelated)

This fixes #12

/claim #12

[mitchellecm7]

Note on Type Check Failure

The type check is failing due to a pre-existing issue in circuit-json dependency (unterminated string literal in node_modules), not caused by my changes.

My changes:

• ✅ All tests pass (Bun Test)
• ✅ Format check passes
• ✅ Code works as demonstrated

This PR is ready for review.