Post-link Vitis pipeline platform for VD100 (XCVE2302). Add new HLS or AIE kernels to the existing Vitis region without starting a new Vivado project. Built from vd100_ma_system_project post-link XSA.

Vitis 2025.2 system project for VD100 (XCVE2302) — v++ link + package for AIE-ML v2 + HLS kernel integration. Produces aie.xclbin and BOOT.BIN CDO artifacts. Reusable: swap AIE kernel or add HLS kernels without new project.

Vitis 2025.2 extensible platform for VD100 (XCVE2302) built from vd100_bd_aie_pipeline XSA. Reusable target for AIE kernel compilation and v++ link. Linux A72 domain. No VCK190 required.

Vivado 2025.2 block design for VD100 (XCVE2302) — CIPS, NoC, AIE-ML v2, AXI interrupt controller, MyLEDIP. Reusable hardware platform for Vitis AIE kernel projects. Exports XSA for vd100_platform. No VCK190 required.

Yocto Scarthgap meta layer for VD100 (XCVE2302) — XRT 2025.2, zocl, AIE-ML v2 pipeline. Fixes undocumented BOOT.BIN CDO gap that leaves all AIE tiles clock-gated under Linux. Submodule of versal-ai-edge-vd100-linux.

Custom Yocto Linux bring-up on Alinx VD100 (XCVE2302). v1: SD/Ethernet/USB. v2: I2C/GPIO/PL LED/kernel driver. v3: XRT + AIE-ML pipeline + Ethereum. No VCK190. No MATLAB. AMD EDF 25.11 / Scarthgap.

Custom Yocto layer for the Alinx VD100 (XCVE2302-SFVA784-1LP-E-S). SD boot, Ethernet, USB, SSH, I2C, LM75, EEPROM, sysmon, and PS LED via libgpiod. AMD EDF 25.11 / Scarthgap. No VCK190 — accessible Versal bring-up on a $1,285 board.

AIE-ML v2 moving average crossover kernel for VD100 (XCVE2302). Dual MA (fast 10 / slow 50 period), BUY/SELL/HOLD signal. 56 int32 samples/iteration via HLS DMA. Used in vd100-aie-pipeline. Vitis 2025.2.