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In versions greater than 2019.2, HLS doesn't generate TLAST signals on AXI Stream busses for the current implementation. Thereby the connection to AXI DMA blocks is broken. Fixed implementation based on HLS stream example from the PYNQ forum: https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344
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Updated overlays and IP build scripts for Vivado/Vitis HLS 2020.2
Fixed IP mult_constant: AXIS Bus had no TLAST signal