Configure PDC to pass through mode for Hamoa#831
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smankad-oss wants to merge 3 commits intoqualcomm-linux:tech/pm/powerfrom
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Configure PDC to pass through mode for Hamoa#831smankad-oss wants to merge 3 commits intoqualcomm-linux:tech/pm/powerfrom
smankad-oss wants to merge 3 commits intoqualcomm-linux:tech/pm/powerfrom
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…nd QMP Document PDC reg to configure pass through or secondary controller mode for GPIO IRQs. Document QMP handle for action concerning global resources. Link: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-2-760c8593ce50@oss.qualcomm.com Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
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maulik-k-shah
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Mar 27, 2026
maulik-k-shah
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maulik-k-shah
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There are two modes PDC irqchip supports pass through mode and secondary controller mode. All PDC irqchip supports pass through mode in which both Direct SPIs and GPIO IRQs (as SPIs) are sent to GIC without latching at PDC. Newer PDCs (v3.0 onwards) also support additional secondary controller mode where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs still works same as pass through mode without latching at PDC even in secondary controller mode. All the SoCs so far default uses pass through mode with the exception of x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK. There is no way to read which current mode it is set to and make PDC work in respective mode as the read access is not opened up for non secure world. There is though write access opened up via SCM write API to set the mode. Configure PDC mode to pass through mode for all x1e based boards via SCM write. Link: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-3-760c8593ce50@oss.qualcomm.com Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
…100 PDC Purwa shares the Hamoa (X1E80100) PDC device, but the hardware register bug addressed in commit e9a48ea ("irqchip/qcom-pdc: Workaround hardware register bug on X1E80100") is already fixed in Purwa silicon. Hamoa compatible forces the software workaround. Add PDC compatible for purwa as "qcom,x1p42100-pdc" to remove the workaround from Purwa. Fixes: f08edb5 ("arm64: dts: qcom: Add X1P42100 SoC and CRD") Link: https://lore.kernel.org/r/20251231-purwa_pdc-v1-1-2b4979dd88ad@oss.qualcomm.com Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
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Application subsystem PDC runs in secondary interrupt controller mode in x1e80100 (Hamoa), while all other targets use pass through mode.
To generalize the behaviour across all targets, set the PDC mode to pass through for Hamoa.
Add the necessary bindings for this.
Also add bindings of PDC compatibility property for Purwa PDC device.
Link:
Hamoa v1: https://lore.kernel.org/all/20260312-hamoa_pdc-v1-0-760c8593ce50@oss.qualcomm.com/
Purwa v1: https://lore.kernel.org/all/20251231-purwa_pdc-v1-0-2b4979dd88ad@oss.qualcomm.com/
Signed-off-by: Maulik Shah maulik.shah@oss.qualcomm.com
Signed-off-by: Sneh Mankad sneh.mankad@oss.qualcomm.com