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    34 repositories

    • heichips25-tapeout

      Public
      HeiChips 2025 Tapeout on IHP SG13G2 130nm process
      Verilog
      •
      Apache License 2.0
      •2•19•13•1•Updated Apr 1, 2026Apr 1, 2026

    • FABulous-bit-gen

      Public
      Bitstream generation for FABulous FPGAs
      Python
      •
      Apache License 2.0
      •3•2•0•0•Updated Mar 31, 2026Mar 31, 2026

    • FABulous-fasm

      Public
      FPGA Assembly (FASM) Parser and Generator
      Python
      •
      Apache License 2.0
      •34•0•0•0•Updated Mar 31, 2026Mar 31, 2026

    • FABulous-demo-projects

      Public
      A Collection of Demo Projects For Testing FABulous
      Verilog
      •
      Apache License 2.0
      •0•2•0•1•Updated Mar 30, 2026Mar 30, 2026

    • FABulous

      Public
      An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
      pythonasicfpga
      pythonasicfpgavhdlverilogefpga
      Python
      •
      Apache License 2.0
      •48•234•58•22•Updated Mar 30, 2026Mar 30, 2026

    • SDF-toolkit

      Public
      Python library for working Standard Delay Format (SDF) Timing Annotation files.
      pythonutilitytoolkits
      pythonutilitytoolkitssdf
      Python
      •
      Apache License 2.0
      •0•1•0•0•Updated Mar 4, 2026Mar 4, 2026

    • FABulousPartialReconfigurationTool

      Public
      CLI tool implementing partial reconfiguration into the open-source FABulous flow
      Python
      •
      Apache License 2.0
      •0•2•0•0•Updated Mar 3, 2026Mar 3, 2026

    • heichips25-template

      Public
      The template for the HeiChips 2025 hackathon
      Tcl
      •
      Apache License 2.0
      •27•6•1•1•Updated Mar 1, 2026Mar 1, 2026

    • f4pga-sdf-timing

      Public
      Python library for working Standard Delay Format (SDF) Timing Annotation files.
      Python
      •
      Apache License 2.0
      •18•0•0•0•Updated Feb 23, 2026Feb 23, 2026

    • byteman

      Public
      Bitstream relocation and manipulation tool.
      C++
      •
      Apache License 2.0
      •5•52•0•0•Updated Feb 20, 2026Feb 20, 2026

    • .github

      Public
      3•0•0•0•Updated Nov 27, 2025Nov 27, 2025

    • FABulousTinyToolbox

      Public
      Collection of small helpfull scripts when working with FABulous
      C++
      •
      Apache License 2.0
      •0•2•0•0•Updated Oct 14, 2025Oct 14, 2025

    • heichips25-workshop

      Public
      HeiChips 2025 LibreLane Workshop
      SystemVerilog
      •
      Apache License 2.0
      •10•14•0•0•Updated Aug 25, 2025Aug 25, 2025

    • heichips25-pcb

      Public
      The official PCB for HeiChips 2025
      Apache License 2.0
      •0•2•2•0•Updated Aug 10, 2025Aug 10, 2025

    • FABulator

      Public
      Fabric generator and CAD tools graphical frontend
      Java
      •
      Apache License 2.0
      •3•18•9•2•Updated Aug 5, 2025Aug 5, 2025

    • FABulous_board

      Public
      A PCB created for FABulous FPGAs, based on the caravel board.
      pcbcaravelfpga-board
      pcbcaravelfpga-board
      Python
      •
      Apache License 2.0
      •1•6•4•3•Updated Jul 18, 2025Jul 18, 2025

    • OWAS

      Public
      Development and integration of a comprehensive open-source ecosystem for the design of complex RISC-V System-on-Chip (SoC) architectures, featuring support for …
      Apache License 2.0
      •0•9•0•0•Updated May 15, 2025May 15, 2025

    • open_eFPGA_v2

      Public
      Verilog
      •
      Apache License 2.0
      •3•20•0•0•Updated Dec 27, 2024Dec 27, 2024

    • FPGA_IGNITE_2024

      Public
      Verilog
      •
      Apache License 2.0
      •1•3•0•0•Updated Nov 29, 2024Nov 29, 2024

    • GoAhead

      Public
      GoAhead
      C#
      •1•5•0•0•Updated Jun 14, 2023Jun 14, 2023

    • OrkhestraFPGAStream

      Public
      Private repository for accelerating DBMS SQL queries with FPGAs
      databasefpga
      databasefpga
      C++
      •
      Apache License 2.0
      •1•8•6•0•Updated Feb 28, 2023Feb 28, 2023

    • nextpnr

      Public archive
      a fork of nextpnr for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream nextpnr
      C++
      •
      ISC License
      •297•1•0•0•Updated Dec 1, 2022Dec 1, 2022

    • FPGA-VS-Web

      Public
      FPGA VIrus Scanner Web Application
      JavaScript
      •1•2•1•0•Updated May 19, 2022May 19, 2022

    • FABulous-Sky---a-heterogeneous-FPGA-fabric-in-Skywater130

      Public
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •370•10•0•0•Updated Nov 19, 2021Nov 19, 2021

    • nextpnr-fabulous

      Public archive
      a fork of nextpnr for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream nextpnr
      C++
      •
      ISC License
      •1•3•0•0•Updated Aug 18, 2021Aug 18, 2021

    • fuserisc

      Public
      Dual RISC-V DISC with integrated eFPGA
      Verilog
      •
      Apache License 2.0
      •5•5•0•0•Updated Jul 16, 2021Jul 16, 2021

    • yosys

      Public archive
      Yosys Open SYnthesis Suite fork for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream yosys…
      C++
      •
      ISC License
      •1.1k•1•0•0•Updated Jun 28, 2021Jun 28, 2021

    • eFPGA---RTL-to-GDS-with-SKY130

      Public
      This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
      Verilog
      •
      Apache License 2.0
      •15•38•2•0•Updated Jun 2, 2021Jun 2, 2021

    • FABulous-SKY130

      Public
      Verilog
      •
      Apache License 2.0
      •2•6•1•0•Updated Apr 28, 2021Apr 28, 2021

    • FPGAVirusScanner

      Public
      Program to scan for malicious FPGA designs.
      Python
      •
      Other
      •5•17•0•1•Updated Mar 20, 2021Mar 20, 2021
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