Adding new interface CEILR and CEILR_ER#2256
Adding new interface CEILR and CEILR_ER#2256prafull-brcm wants to merge 2 commits intoopencomputeproject:masterfrom
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| SAI_PORT_INTERFACE_TYPE_USXGMII, | ||
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| /** Interface type CEILR */ | ||
| SAI_PORT_INTERFACE_TYPE_CEILR, |
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could you please clarify which technology is meant here ?
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This is optical common electrical interface for LR as normal reach and LR_ER for extended reach optical cables for ethernet lane data rate 56G, 112G, 212G etc .
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Is it some proprietary technology or standard one ?
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CEILR is OIF standard electrical interface for backplane copper cable to connect module to module or chip to chip.
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@prafull-brcm - are you able to discuss this in the SAI community meeting on 3/12? |
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@tjchadaga I can discuss this on 3/12 meeting in SAI community meeting. |
Adding new electrical interface CEILR for normal reach and CEILR_ER to enable extended reach option in SERDES. Signed-off-by: Prafull Singh <56103377+prafull-brcm@users.noreply.github.com>
Signed-off-by: Prafull Singh <56103377+prafull-brcm@users.noreply.github.com>
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CEIMR interface is added for medium reach interconnect cable < 30cm length to connect chip to chip on same PCB.
CEILR and CEILR_ER (extended reach) interface is added to connect with cable (twin-axial copper cable backplane) < 1 m for communication interface between two cards across a backplane.
These interfaces follows OIF’s (Optical Internetworking Forum ) Common Electrical Interface.
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Adding new electrical interface CEILR for normal reach and CEILR_ER to enable extended reach option in SERDES.