GitHub - maciejkwasek/uart_loop: VHDL training · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
constraints		constraints
rtl		rtl
sim		sim
tb		tb
.gitignore		.gitignore
uart_loop.qpf		uart_loop.qpf
uart_loop.qsf		uart_loop.qsf

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VHDL training

fpga vhdl quartus-prime vhdl-examples cyclone-10lp vhdl-uart

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VHDL 100.0%