ZynqMP I2C Driver

[SeedRizvi]

General

This PR adds an I2C driver for the ZynqMP platform, tested on the Kria K26 board using the i2c_bus_scan example. Made in collaboration with @potanin.

The driver follows the structure of the existing OpenTitan I2C driver and was implemented by referencing the Xilinx I2C driver and TRM.

Configuration	Value	Notes
SCLK frequency	400 kHz	Fast mode
FIFO depth	16 bytes	Hardware fixed
Addressing mode	7-bit	Normal addressing
I2C Bus	I2C1	Contains ZynqMP Hw, work with i2c_bus_scan test without external Hw
Max transfer size (writes)	N/A	Writes to FIFO in FIFO_DEPTH chunks until request is fulfilled
Max transfer size (reads)	252 bytes	Hardware limti of tf_size register. Larger reads are queued through FSM.

Limitations

• Support for I2C Write operations > 16 bytes exists, but has not been tested as I simply do not have the hardware on our carrier board. Which has the ZynqMP EEPROM on I2C1, and a custom temperature sensor on I2C0 using only 2-byte writes.

Differences from OpenTitan

• WRRD (write-read) handling: The ZynqMP I2C controller requires explicit two-phase WRRD (2 I2C operations) with HOLD set during the subaddress write, followed by a repeated START for the read phase. This is managed via the await_wrrd state machine (WRRD_WRADDR -> WRRD_SUBADDR -> read).
• Receive transfer size: Supports > 252 byte reads in master receive mode. Transfers exceeding 252 bytes are chunked across multiple FIFO loads with HOLD maintained.
• Bus busy detection: setup_master() checks bus activity before initiating transfers with HOLD-aware logic to avoid false positives during multi-phase operations.

Other

I have refrained from adding ZCU102 to the i2c_bus_scan example as I haven't tested it, but it would be nice to do that as part of this PR.