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This implementation includes all clock definitions, basic operations of clock compoents, as well as interfaces to interact with clicnets via PPC. Client should be able to enable/disable a specific gate clock or query the current clock rate by passing the corresponding clock identifier, which is listed in g12a-bindings.h. set_rate() assumes that the rate requst is valid and compatible with the current configurations. Complete implementation that considers more incompatible requests will come in the future when dynamic clock configuration is necessary in lionsos Signed-off-by: Terry Bai <terry.z.bai@gmail.com> add Makefile Signed-off-by: Terry Bai <terry.z.bai@gmail.com> Clock driver for maaxboard Add clock driver for maaxboard. This commit includes all clock component definitions, basic operations, and a simple test on maaxboard. Scripts are added in build systems. A few files are reorganised for reuse Signed-off-by: Terry Bai <terry.z.bai@gmail.com> Clk: fix style Signed-off-by: Terry Bai <terry.z.bai@gmail.com> clk: modify interfaces and fix issues during initialisation This commit includes modifiation to the interfaces, primarily for set/get rate, which return error state as well as final rate. More tests are conducted to verify the basic operations of types of clock components. A few bugs are fixed as well. Signed-off-by: Terry Bai <terry.z.bai@gmail.com> clk: fix style and add licenses This commit fixed style and license issues Signed-off-by: Terry Bai <terry.z.bai@gmail.com> clk: fix style and data types This commit replaces all platform-dependent data types with fix-sized types, and unifies the return values of interfaces as signed integers. The return value 0 indicates the success on the request to clock driver, and negative values indicate the failure reasons. Signed-off-by: Terry Bai <terry.z.bai@gmail.com> clk: combine regmap_* and regmap_mux_* operations Abstract a set of regmap_* operations by combining mux-specific ones and ordinary ones Signed-off-by: Terry Bai <terry.z.bai@gmail.com> clk: add get/set parent interfaces Add clk_get_parent() and clk_set_parent() interfaces for the clients. Fixed several logic issues in related implementations. More clock component definition checkings and fixup. Signed-off-by: Terry Bai <terry.z.bai@gmail.com> clk: set_rate for maaxboard clocks This commit adds set_rate() implementations for maaxboard. Now clocks can be set to target rate at initialisation time and configured dynamically. Signed-off-by: Terry Bai <terry.z.bai@gmail.com> clk: reorganise files This commit reorgnises source files to allow more code to be shared for multiple boards. Refactor makefiles: - move objectives to clk_driver directory - use built-in CFLAGS in rules Temporary fixup for a zig build issue: create_clk_config.py cannot find the lazypath `zig-out/bin` when executing. The current solution is to create an install directory in advance, but it would be a bit of trouble to find the generated header file if someone want to read or modify it. Moved clock specifier binding files to `include/sddf/clk`, so the clients will be able to configure clocks with macro constants Signed-off-by: Terry Bai <terry.z.bai@gmail.com> Update clock driver to current sddf build style, added meta.py Signed-off-by: Lesley Rossouw <lesley.rossouw@unsw.edu.au> Replace setvar constants, move all memory region setup to meta.py Signed-off-by: Lesley Rossouw <lesley.rossouw@unsw.edu.au> Clock driver for maaxboard Add clock driver for maaxboard. This commit includes all clock component definitions, basic operations, and a simple test on maaxboard. Scripts are added in build systems. A few files are reorganised for reuse Signed-off-by: Terry Bai <terry.z.bai@gmail.com> examples/clk: remove timer for client Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au> examples/clk: remove dts dir Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au> drivers/clk: add sddf_clk_set_cpu_freq() interface Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au> drivers/clk: add ARM_CLK and remove sddf_clk_set_cpu_freq() Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au> clock driver hotfixes Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au> clk driver flake dep Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
…as we think the peripheral clocks are gated Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
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Written to help out lesley for NCSC. as such, not complete and the details of the protocol are not fixed.
Includes the pinctrl and clock drivers as squashed commits.
Tested with the logic analyser, it can maintain the frequencies and period setpoints I tested.