FPGA-Design

This repository gathers basic knowledge of how to build circuits using VHDL and Verilog description languages. The circuits implemented are:

Full adder 1 Bit

Full adder N bits (4 Bits)

Comparator 1 Bit

Comparator N Bits

Synchronous Binary Counter

Memory

Single Port RAM

Dual Port RAM

FIFO

FSM

ALU