VHDL Programming Repository

This repository contains different VHDL projects for learning and practicing digital design, FSMs, arithmetic units, and CPU implementation.

Table of Contents

1. Basic Gates
2. Half Adder
   • Structural Modelling
3. Full Adder
   • Behavioral Modelling
   • Dataflow Modelling
4. Multiplexer
   • 4 x 1 Mux
   • 16 x 1 Mux
5. Demultiplexer
6. Encoder
   • 4 x 2 Encoder
   • 8 x 3 Priority Encoder
7. Decoder
   • 3x8 Decoder
8. 4-bit Ripple Carry Adder (Board Implementation)
9. Interfacing Seven Segment Display using VHDL(Board Implementation
10. Arithmetic Logic Unit(ALU) into FPGA
11. Moore based Sequence Detector FSM
    • Moore “01” Sequence Detector
12. Melay based Sequence Detector FSM
    • Mealy “01” Sequence Detector
13. Counters
    • 8-bit Up Down counter with Synchronous Reset and Load
    • 8-bit Up Down counter with Asynchronous Reset and Synchronous Load
14. Shift Register
    • 8-bit Universal Shift Register with Asynchronous Reset and Synchronous Load
    • 8-bit Universal Shift Register with Synchronous Reset and Load
    • 4-bit Shift Register
15. Accelerometer

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Semster Project - Digital Clock using Artix-7 100T FPGA board

This project is a 24-hour Digital Clock implemented using VHDL and tested on the Nexys A7-100T FPGA board. It displays real-time hours, minutes, and seconds using a 6-digit 7-segment display. This is not a typical learning exercise—it's a complete semester project submitted for academic evaluation at HNB Garhwal University, under the subject Digital System Design using VHDL.

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🛠️ Tools Used

• Xilinx Vivado (Simulation & FPGA Implementation)
• ModelSim (Functional & Timing Simulation)
• Icarus Verilog (For Open source compilation)
• GHDL & GTKWave (For Open-Source Simulation)
• Artix-7 Nexys A7-100T (FPGA Board for Hardware Testing)

🤝 Contributions

Feel free to fork this repo, add improvements, and submit PRs!

📬 Contact

For queries, reach out on LinkedIn: Swaroop Kumar Yadav