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AVX-512 support#80

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Shnatsel wants to merge 6 commits intomainfrom
avx512
Draft

AVX-512 support#80
Shnatsel wants to merge 6 commits intomainfrom
avx512

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@Shnatsel
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@Shnatsel Shnatsel commented Feb 22, 2026

Draft because it needs a non-mainline fearless_simd

performance numbers: https://gist.github.com/Shnatsel/9b64215c8f7372bb6362c3650101b0f2

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codecov-commenter commented Feb 22, 2026

Codecov Report

❌ Patch coverage is 50.00000% with 2 lines in your changes missing coverage. Please review.
✅ Project coverage is 98.97%. Comparing base (e9d8850) to head (ca4fa63).

Files with missing lines Patch % Lines
src/algorithms/bravo.rs 50.00% 2 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main      #80      +/-   ##
==========================================
- Coverage   99.10%   98.97%   -0.13%     
==========================================
  Files          10       10              
  Lines        1566     1568       +2     
==========================================
  Hits         1552     1552              
- Misses         14       16       +2     

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@Shnatsel
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I looked into the regressions for small sizes. They regress because we fall back to scalar bit reversal since BRAVO operates on LANES * LANES blocks.

I've tried adapting BRAVO to work on smaller sizes, and while I got that to be correct I didn't get any performance benefits from that.

There are two things we could do here:

  1. Fall back to a BRAVO implementation with a smaller vector size
  2. Optimize the scalar bit reversal

We should probably do both. We already have a menagerie of bit reversal methods from our earlier experiments.

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