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PreethamSK163/README.md

MAC Unit Netlist (Patent)  ·  RISC-V Core (Makerchip)  ·  Semiconductor Packaging (ANSYS)  ·  GDSII Layout (Magic VLSI)

Preetham SK

Aspiring VLSI Engineer  ·  B.Tech EEE @ VIT Chennai  ·  MS Applicant — Germany 🇩🇪

   

I am a final-year B.Tech EEE student at VIT Chennai, working towards a career in VLSI and planning to pursue a Master's degree in Germany. Over the past two years I have completed 6 projects spanning RTL design, physical design, EDA automation, and semiconductor packaging — along with 6 publications including 2 patents, 2 SCI journal papers, and a book chapter with CRC Press. I have also done internships at CNVD VIT, CSGT VIT, Maven Silicon, and SkillDzire.

Publications & Patents

Type Details
🏛️ Patent [Published] Dynamic Reconfigurable Binary Multiplier — App. No. 202541080342, Published Sep 2025
🏛️ Patent [Under Review] Low Power VLSI Design — Preetham SK (First Inventor)
📰 SCI Journal [Under Review] 16-Bit MAC Unit — Preetham SK (First Author)
📰 SCI Journal [Under Review] Low Power VLSI Design — Preetham SK (Second Author)
📖 Book Chapter [Accepted] FPGA Based Solar Powered EV Charging Station — CRC Press, Taylor & Francis (ISBN: 9781041093626)
📰 Research Article [Under Review] CNN Application — Preetham SK (First Author)

Projects

# Project Tools
01 Digital VLSI SoC Design & Planning — RTL-to-GDSII on PicoRV32a; custom cell integration; ECO timing closure; DRC/LVS clean Verilog, OpenLANE, Sky130 PDK, Magic VLSI
02 RISC-V CPU Design using TL-Verilog — 5-stage pipelined RV32I core; hazard bypassing; verified on Makerchip TL-Verilog, Makerchip
03 VLSI Design Automation Using TCL — VSDSYNTH — Automated RTL-to-QoR framework; 6845 gates on openMSP430 TCL, Yosys, OpenTimer, Linux
04 SPI Physical Design using Qflow — 3106 cells, 22417 routes; DRC/LVS clean; GDSII generated Qflow, Yosys, Magic, Netgen
05 RTL Digital Design Modules using Verilog — UART, FIFO, Traffic Light, ATC, Washing Machine Verilog HDL, ModelSim
06 Packaging Design and Simulation using ANSYS — Thermal & thermo-mechanical analysis; flip-chip BGA, QFN ANSYS Electronics Desktop

Certifications

Certification Details
🏅 CeNSE Winter School on Semiconductor Technology Certificate of Distinction — IISc Bengaluru, Dec 2025
🎓 Chip-based VLSI Design for Industrial Applications Specialisation — L&T EduTech via Coursera, Sep 2025
📋 RISC-V Processor — RV32I Base ISA Maven Silicon, Feb 2025

Skills

Category Tools
Languages Verilog HDL, TL-Verilog, TCL, C, Python
EDA Tools OpenLANE, Yosys, Magic VLSI, Qflow, Cadence NC Launch, Cadence Genus, ModelSim, Netgen, OpenTimer, HSPICE, LT Spice
Simulation ANSYS Electronics Desktop, ANSYS Mechanical, Makerchip IDE
Platforms Linux, Windows

Popular repositories Loading

  1. Project-1-Digital-VLSI-SoC-Design-and-Planning Project-1-Digital-VLSI-SoC-Design-and-Planning Public

    RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC…

  2. Project-3-VLSI-Design-Automation-Using-TCL-VSDSYNTH Project-3-VLSI-Design-Automation-Using-TCL-VSDSYNTH Public

    A fully automated, design-agnostic RTL-to-QoR synthesis and timing analysis framework built using TCL — integrating Yosys and OpenTimer through CSV-driven configuration, SDC constraint generation, …

    Tcl

  3. Project-6-Packaging-Design-and-Simulation-using-ANSYS Project-6-Packaging-Design-and-Simulation-using-ANSYS Public

    A hands-on exploration of semiconductor packaging — covering package types, ATMP processes, thermal simulation of flip-chip BGA packages, reliability testing, and 3D package cross-section modeling …

  4. Project-2-RISC-V-CPU-Design-using-TL-Verilog Project-2-RISC-V-CPU-Design-using-TL-Verilog Public

    A hands-on implementation of a RISC-V CPU — progressing from ISA fundamentals and GNU toolchain to a fully functional 5-stage pipelined processor with hazard resolution, bypassing, and memory opera…

    TL-Verilog

  5. Project-4-SPI-Physical-Design-using-Qflow Project-4-SPI-Physical-Design-using-Qflow Public

    A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LV…

  6. Project-5-RTL-Digital-Design-Modules-using-Verilog Project-5-RTL-Digital-Design-Modules-using-Verilog Public

    A collection of 5 RTL digital design modules implemented in Verilog and simulated using ModelSim — covering UART, FIFO, Traffic Light Controller, Automatic Temperature Control, and Washing Machine …

    Verilog