This repository contains advanced VLSI design projects focused on digital filtering and signal processing. It is organized into two main projects:
- Project 1: 102-Tap FIR Filter Implementation – Demonstrates various FIR architectures (traditional, pipelined, parallel processing) to meet stringent performance specifications.
- Final Project: Digital Equalizer with Pipelined 4th Order IIR Filter – Implements a digital equalizer comparing a pipelined IIR filter to a traditional design for real-time audio processing.
This repository showcases advanced VLSI methodologies implemented with MATLAB, Python, and Verilog. It emphasizes:
- High-Performance Digital Filter Designs: Techniques include quantization, overflow management, pipelining, and parallel processing.
- Robust Simulation and Synthesis: Detailed simulation setups and synthesis reports (area, timing, and power metrics) are provided.
- Modular Code Architecture: Reusable, parameterized Verilog modules and automated coefficient generation scripts.
This repository is structured to showcase:
- Clear Documentation: Detailed explanations of design trade-offs and simulation results.
- Modular Code: Scalable, parameterized Verilog designs.
- Professional Analysis: A critical evaluation of performance metrics and hardware implementation results.
🔗 Live Demo: GitHub Pages
🌐 Website: paulnieves.com
📧 Contact: nievep@rpi.edu