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[Frontend] Use ops instead of raw assembly code
…dening errors Updated the frontend to strictly validate vector element counts, preventing invalid LMUL=8 configurations in Gem5. Fixed a mismatch in the ext() operation's type-checking logic.
…ftmax Note: Known compilation errors persist when using smaller tile sizes; investigation into the tile-stride logic is ongoing.
[FIX] Fix zero systolic array utilization during SDPA execution
Feat/deepseek
-Update Ramulator version to 2.1 -Update Ramulator2 DRAM configs
… demand in docker-image workflow
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Changelog —
develop→masterTOGSim (simulator)
Compiler & runtime (PyTorchSim / MLIR)
torch.nn.attention.sdpa_kernel([SDPBackend.FLASH_ATTENTION])context manager; TopK, Bitonic sort, Cat added. ([BUG]Support for repeat_interleave operation to enable Grouped Query Attention (GQA) #198)lmul8widening issue by avoiding the problematic vector-width in codegen.with TOGSimulator(config_path=...):so config and simulator lifecycle are scoped to the block.torch.npu.launch_model(opt_fn, *args, stream_index=..., timestamp=..., **kwargs)inside that block.Device (OpenReg / NPU)
torch.device("npu")(andtorch.device("npu:0"), etc.) like any built-in device type — no extra package import beyondimport torch; the NPU backend registers with PyTorch's device system.eager_to_compile()API provided for explicit transition.Schedulerinstantiation,Requestobject construction, and awhile not scheduler.is_finished():loop. The new API uses awith TOGSimulator(config_path=...):context andtorch.npu.launch_model(..., stream_index=..., timestamp=...)calls directly. Seetest_scheduler.pyfor the updated usage pattern.CI, tests, experiments
Other