Transitioning from foundational electronics to advanced computer architecture. Passionate about designing and verifying the next generation of silicon.
- 🔭 Currently Building: A Constrained-Random Verification Testbench for a 32-bit ALU.
- 🌱 Currently Learning: SystemVerilog, UVM, and AMBA AXI4 Protocols.
- 📫 Reach me at: nikunjbhatt244@gmail.com
Hardware Description & Verification:
Scripting & Modeling:
EDA Tools & FPGAs:
- 4-Stage Pipelined Processor: Architected a custom processor core in Verilog implementing instruction fetch, decode, execute, and write-back stages with custom hazard detection and data forwarding logic to eliminate pipeline stalls. Synthesized using Synopsys DC.
- 32-Bit ALU with Zero-Flag Logic: Designed and verified a 32-bit ALU supporting complex arithmetic/logical ops. Validated via exhaustive ModelSim testbenches.