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video: improve vsync#94

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tiopex merged 3 commits intoMiyooCFW:masterfrom
tiopex:vsync2
Jul 5, 2025
Merged

video: improve vsync#94
tiopex merged 3 commits intoMiyooCFW:masterfrom
tiopex:vsync2

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@tiopex
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@tiopex tiopex commented Jul 2, 2025

Improve vsync feature:

  • Improvement performance for Tefix 2 and 3
  • Works for all CPU speeds

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@Apaczer Apaczer left a comment

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Great! This is much better (no weird scanlines on top-right), also performance differse little between tefix variants:

new-tefix=0 (223fps)
new-tefix=1 (209fps)
new-tefix=2 (204fps)
new-tefix=3 (202fps)

10% gain for 2&3 tefix compering to former code 👍

lcdc_wr_cmd(0x45);
lcdc_rd_dat();
lcdc_rd_dat();
mycpu_clock = readl(iomm.ccm + PLL_CPU_CTRL_REG);
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considering we remove PLL_CPU_CTRL_REG condition, do you think we should just leave tefix=2 (since it's more performant?) and dump tefix=3. AFAIR we had those two for either overclocking or underclocking CPUfreq.

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@tiopex tiopex Jul 3, 2025

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As far as I remember, some panels couldn't handle tefix 3 (or 2?) — for those, tefix 2( or 3?) with a reduced clock in the panel was used

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tefix=2 or 3 was running with 96MHz (0x91001303), but now we will use 108MHz (tefix=2) & 114MHz (tefix=3) from what I see. Will this be ok for those inferior panels?

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ah I believe 0x91001303 is 120MHz so much higher than current clocks

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@tiopex tiopex Jul 4, 2025

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Indeed tcon clock increased but panel clock was lowered

lcdc_wr_cmd(0xc6);
if (tefix == 3)
lcdc_wr_dat(0x04);
else if (tefix == 2)
lcdc_wr_dat(0x05);

@tiopex tiopex merged commit f31e12c into MiyooCFW:master Jul 5, 2025
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2 participants