[codex] Restore pyc5 example gate after hengliao/main merge#48
[codex] Restore pyc5 example gate after hengliao/main merge#48
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… OoO core pycc backend: - Add --hierarchical / --flatten CLI flags for Verilog output mode - New FlattenInstancesPass to inline all pyc.instance ops for flat output - --hierarchical preserves domain.call() boundaries as separate Verilog modules - --flatten inlines all sub-modules into a single top-level module V5 frontend fixes: - Auto-stamp pycc metadata (pyc.kind, pyc.struct.metrics, etc.) on all func.func in hierarchical mode via _make_compiled_module - Fix output dict reconstruction: use actual result port indices instead of positional matching (fixes field-major vs slot-major ordering mismatch) - Auto-insert zext/trunc in _call_hierarchical when input signal widths don't match sub-module port widths Documentation: - Merge V5 API reference + tutorial into single PyCircuit_V5_Spec.md - Add RTL compilation flow section with full pycc CLI reference - Document hierarchical and flatten build pipelines with Davinci examples - Update all cross-references to point to new unified spec Davinci OoO Core: - Add outerCube/davinci design tree (14 sub-modules) - Generated Verilog: flat (39K lines) and hierarchical (14 modules, 65K lines) Made-with: Cursor
- Remove build_ prefix from all function names (43 files) - Convert XiangShan-pyc compositing modules to domain.call() (8 modules) - Enhance V5 frontend: auto-propagate unmatched sub-module ports, canonical-prefix compilation for multi-instance caching - Add build_all.py + build_design.py build tools - Include hierarchical Verilog output for all designs (xs_top: 40 modules/546K lines, davinci: 15 modules/65K lines) Made-with: Cursor
# Conflicts: # compiler/frontend/pycircuit/v5.py # designs/examples/bundle_probe_expand/bundle_probe_expand.py # designs/examples/digital_filter/digital_filter.py # designs/examples/trace_dsl_smoke/trace_dsl_smoke.py
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Code Review
This pull request introduces hierarchical compilation support for the V5 circuit builder, adds a ForwardSignal type for more ergonomic register assignment, and includes a new FlattenInstancesPass in the MLIR compiler. My review identified a critical bug in the ForwardSignal import logic within jit.py that would cause a TypeError at runtime, and noted an inconsistency regarding the public API's removal of direct .wire access, which is still exposed as a property on CycleAwareSignal and ForwardSignal.
| try: | ||
| from .v5 import ForwardSignal | ||
| except Exception: | ||
| ForwardSignal = () # type: ignore[assignment] | ||
| if isinstance(cur, Reg): | ||
| cur <<= rhs | ||
| self.env[name] = cur | ||
| return | ||
| if isinstance(cur, ForwardSignal): | ||
| cur <<= rhs | ||
| self.env[name] = cur | ||
| return | ||
| raise JitError( | ||
| "<<= is only supported for Reg or ForwardSignal variables" | ||
| ) |
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The try-except block for importing ForwardSignal has a latent bug. If the import fails, ForwardSignal is assigned an empty tuple (). Later, isinstance(cur, ForwardSignal) becomes isinstance(cur, ()), which will raise a TypeError because the second argument to isinstance must be a type or a tuple of types.
Additionally, the logic for handling Reg and ForwardSignal is duplicated. You can refactor this to be more robust and concise by combining the checks.
try:
from .v5 import ForwardSignal
except Exception:
ForwardSignal = None
supported_types = (Reg, ForwardSignal) if ForwardSignal is not None else (Reg,)
if isinstance(cur, supported_types):
cur <<= rhs
self.env[name] = cur
return
raise JitError(
"<<= is only supported for Reg or ForwardSignal variables"
)| @property | ||
| def wire(self) -> Wire: | ||
| return self._w |
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The docstring for wire_of (lines 752-761) states that "Direct .wire access is removed from the public API." However, the wire property is still present on CycleAwareSignal (and ForwardSignal at lines 624-625). This is inconsistent with the stated goal and with the removal of this property from StateSignal.
To enforce using wire_of and maintain consistency, you should consider removing the wire property from CycleAwareSignal and ForwardSignal.
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Summary
hengliao/mainupdate onto the pyc5 example/gate surface without breaking the V5/JIT contractForwardSignal/state usage in the frontend so signal-based examples compile againdocs/gates/logs/codex-examples-20260407-r5/Validation
PYC_GATE_RUN_ID=codex-examples-20260407-r5 bash flows/scripts/run_examples.shdocs/gates/logs/codex-examples-20260407-r5/