WIP - fix[cartesian]: loop reordering in schedule tree#2546
Draft
romanc wants to merge 2 commits intoGridTools:mainfrom
Draft
WIP - fix[cartesian]: loop reordering in schedule tree#2546romanc wants to merge 2 commits intoGridTools:mainfrom
romanc wants to merge 2 commits intoGridTools:mainfrom
Conversation
romanc
force-pushed
the
romanc/fix-k-loop-flipping
branch
from
10f824c to
c1a3422
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Description
This PR fixes the loop reordering in the schedule tree. Loop reordering is used as part of the automatic adaption to different memory layouts. The current implementation would run into issues when re-ordering sequential vertical loops (e.g.
with computation(FORWARD)orwith computation(BACKWARD)).The issue is part of an ongoing effort to stabilize/validate the remapping translate test with different loop/memory layouts.
Requirements
N/A