GitHub - AngelTerrones/Basic-verilog-project: Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
rtl		rtl
scripts		scripts
test		test
ucf		ucf
.gitignore		.gitignore
Makefile		Makefile

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Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

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