GitHub - AkshayRaj/MIPS_PipeLine_Simulator: This Project simulates the workings of a 4 stage MIPS PipeLine. The Simulator writes the Cycle Number when an instruction leaves a PipeLine Stage. It detects RAW, WAW, WAR and Structural Hazards Accurately. A two level Memory Hierarchy is also implemented in the PipeLine. Cache hits and Misses for both I-Cache and D-Cache are also written on the Scoreboard.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Cache.java		Cache.java
EX.java		EX.java
Hazard.java		Hazard.java
ID.java		ID.java
IF.java		IF.java
Locks.java		Locks.java
PipeLine.java		PipeLine.java
Scoreboard.java		Scoreboard.java
Simulator.java		Simulator.java
WB.java		WB.java

About

This Project simulates the workings of a 4 stage MIPS PipeLine. The Simulator writes the Cycle Number when an instruction leaves a PipeLine Stage. It detects RAW, WAW, WAR and Structural Hazards Accurately. A two level Memory Hierarchy is also implemented in the PipeLine. Cache hits and Misses for both I-Cache and D-Cache are also written on the…