diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/Readme.md b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/Readme.md new file mode 100644 index 0000000000..048e474142 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/Readme.md @@ -0,0 +1,116 @@ +# oneAPI SYCL HLS Gaskets + +The two Platform Designer IPs in this repository simplify the process of using oneAPI video IPs with the existing [Intel Video and Vision Processing (VVP)](https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/dsp/video-vision-processing-suite.html) IP suite. + +These gaskets should be placed on either side of a oneAPI IP to adapt the AXI4-Streaming physical layer used by the VVP IPs to the Avalon Streaming physical layer used by the oneAPI IPs. + +![oneAPI gaskets flanking a oneAPI streaming IP](assets/schematic.png) + +## Description + +These gaskets do NOT do any protocol conversion, they simply route the sideband signals as follows: + +| AXI4-Streaming Signal | Avalon Streaming Signal | +|-----------------------|-------------------------| +| `tready` | `ready` | +| `tvalid` | `valid` | +| `tdata` | `data` | +| `tlast` | `endofpacket` | +| `tuser[0]` | `startofpacket` | + +Furthermore, these gaskets also adapt the padding between pixels used in the VVP video protocol to match the padding requirements imposed by limitations of SYCL HLS. SYCL HLS inserts padding bits after each *color channel*, while the AXI4-Streaming video protocol requires padding only be inserted after each *pixel*. The IPs in this repository adapt the pixels appropriately. + +**oneAPI Padding** + +![](assets/SYCL_HLS_padding.png) + + +**VVP Padding** + +![](assets/VVP_Padding.png) + +## Usage + +You can add these IPs to a Platform Designer system easily. When you instantiate an IP, you will see a parameter editor screen like this: + +![](assets/parameters.png) + +Set the `Parallel Pixels`, `Color Channels`, and `Bits per Channel` properties to match the parameterizations of your VVP IPs. The Avalon interfaces will automatically be calculated. You can view the intermediate calculations by ticking the `Show Derived Parameters` check box, or by inspecting the `Signals and Interfaces` tab under `Component Instantiation`. + +![](assets/signals-and-interfaces.png) + +Here is an example of how to connect up the IPs in the Platform Designer patch panel: + +![](assets/patch-panel.png) + +## Testing + +This IP includes a simple testbench that you can run with Questasim using the included `test.do` script: + +``` +vsim -c -do test_avalon_to_axi.do +``` + +The output looks like: + +``` +# PARALLEL_PIXELS = 2 +# BITS_PER_CHANNEL = 10 +# CHANNELS = 3 +# BITS_PER_CHANNEL_AV = 16 +# BITS_PER_PIXEL_AV = 48 +# BITS_AV = 96 +# EMPTY_BITS = 4 +# BITS_PER_CHANNEL_AXI = 10 +# BITS_PER_PIXEL_AXI = 32 +# BITS_AXI = 64 +# TUSER_BITS = 8 +# TUSER_FILL = 6 +# MASK_OUT = 000003ff +# cin 0b0 | reset_n 0b0 | axm_tready 0bx | axm_tvalid 0bx | axm_tdata 0xXxxxxxxxXxxxxxxx | axm_tlast 0xx | axm_tuser 0x0X | asi_ready 0bx | asi_valid 0bx | asi_data 0xxxxxxxxxxxxxxxxxxxxxxxxx | asi_sop 0bx | asi_endofpacket 0bx | asi_empty 0bxxxx +# cin 0b1 | reset_n 0b0 | axm_tready 0bx | axm_tvalid 0bx | axm_tdata 0xXxxxxxxxXxxxxxxx | axm_tlast 0xx | axm_tuser 0x0X | asi_ready 0bx | asi_valid 0bx | asi_data 0xxxxxxxxxxxxxxxxxxxxxxxxx | asi_sop 0bx | asi_endofpacket 0bx | asi_empty 0bxxxx +# cin 0b0 | reset_n 0b1 | axm_tready 0bx | axm_tvalid 0bx | axm_tdata 0xXxxxxxxxXxxxxxxx | axm_tlast 0xx | axm_tuser 0x0X | asi_ready 0bx | asi_valid 0bx | asi_data 0xxxxxxxxxxxxxxxxxxxxxxxxx | asi_sop 0bx | asi_endofpacket 0bx | asi_empty 0bxxxx +# cin 0b1 | reset_n 0b1 | axm_tready 0bx | axm_tvalid 0bx | axm_tdata 0xXxxxxxxxXxxxxxxx | axm_tlast 0xx | axm_tuser 0x0X | asi_ready 0bx | asi_valid 0bx | asi_data 0xxxxxxxxxxxxxxxxxxxxxxxxx | asi_sop 0bx | asi_endofpacket 0bx | asi_empty 0bxxxx +# cin 0b0 | reset_n 0b1 | axm_tready 0b1 | axm_tvalid 0b1 | axm_tdata 0x0230882101304811 | axm_tlast 0x0 | axm_tuser 0x00 | asi_ready 0b1 | asi_valid 0b1 | asi_data 0x002300220021001300120011 | asi_sop 0b0 | asi_endofpacket 0b0 | asi_empty 0bxxxx +# cin 0b1 | reset_n 0b1 | axm_tready 0b1 | axm_tvalid 0b1 | axm_tdata 0x0230882101304811 | axm_tlast 0x0 | axm_tuser 0x00 | asi_ready 0b1 | asi_valid 0b1 | asi_data 0x002300220021001300120011 | asi_sop 0b0 | asi_endofpacket 0b0 | asi_empty 0bxxxx +# ** Note: $stop : test_avalon_to_axi.sv(120) +# Time: 30 ns Iteration: 1 Instance: /test_avalon_to_axi +# Break at test_avalon_to_axi.sv line 120 +# Stopped at test_avalon_to_axi.sv line 120 +# End time: 07:29:43 on Apr 08,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +``` + +``` +vsim -c -do test_axi_to_avalon.do +``` + +The output should look like: + +``` +# PARALLEL_PIXELS = 2 +# BITS_PER_CHANNEL = 10 +# CHANNELS = 3 +# BITS_PER_CHANNEL_AV = 16 +# BITS_PER_PIXEL_AV = 48 +# BITS_AV = 96 +# EMPTY_BITS = 4 +# BITS_PER_CHANNEL_AXI = 10 +# BITS_PER_PIXEL_AXI = 32 +# BITS_AXI = 64 +# TUSER_BITS = 8 +# TUSER_FILL = 6 +# MASK_OUT = 000003ff +# cin 0b0 | reset_n 0b0 | axs_tready 0bx | axs_tvalid 0bx | axs_tdata 0xxxxxxxxxxxxxxxxx | axs_tlast 0xx | axs_tuser 0xxx | aso_ready 0bx | aso_valid 0bx | aso_data 0x0Xxx0Xxx0Xxx0Xxx0Xxx0Xxx | aso_sop 0bx | aso_endofpacket 0bx | aso_empty 0b0000 +# cin 0b1 | reset_n 0b0 | axs_tready 0bx | axs_tvalid 0bx | axs_tdata 0xxxxxxxxxxxxxxxxx | axs_tlast 0xx | axs_tuser 0xxx | aso_ready 0bx | aso_valid 0bx | aso_data 0x0Xxx0Xxx0Xxx0Xxx0Xxx0Xxx | aso_sop 0bx | aso_endofpacket 0bx | aso_empty 0b0000 +# cin 0b0 | reset_n 0b1 | axs_tready 0bx | axs_tvalid 0bx | axs_tdata 0xxxxxxxxxxxxxxxxx | axs_tlast 0xx | axs_tuser 0xxx | aso_ready 0bx | aso_valid 0bx | aso_data 0x0Xxx0Xxx0Xxx0Xxx0Xxx0Xxx | aso_sop 0bx | aso_endofpacket 0bx | aso_empty 0b0000 +# cin 0b1 | reset_n 0b1 | axs_tready 0bx | axs_tvalid 0bx | axs_tdata 0xxxxxxxxxxxxxxxxx | axs_tlast 0xx | axs_tuser 0xxx | aso_ready 0bx | aso_valid 0bx | aso_data 0x0Xxx0Xxx0Xxx0Xxx0Xxx0Xxx | aso_sop 0bx | aso_endofpacket 0bx | aso_empty 0b0000 +# cin 0b0 | reset_n 0b1 | axs_tready 0b1 | axs_tvalid 0b1 | axs_tdata 0xc2308821c1304811 | axs_tlast 0x0 | axs_tuser 0x00 | aso_ready 0b1 | aso_valid 0b1 | aso_data 0x002300220021001300120011 | aso_sop 0b0 | aso_endofpacket 0b0 | aso_empty 0b0000 +# cin 0b1 | reset_n 0b1 | axs_tready 0b1 | axs_tvalid 0b1 | axs_tdata 0xc2308821c1304811 | axs_tlast 0x0 | axs_tuser 0x00 | aso_ready 0b1 | aso_valid 0b1 | aso_data 0x002300220021001300120011 | aso_sop 0b0 | aso_endofpacket 0b0 | aso_empty 0b0000 +# ** Note: $stop : test_axi_to_avalon.sv(120) +# Time: 30 ns Iteration: 1 Instance: /test_axi_to_avalon +# Break at test_axi_to_avalon.sv line 120 +# Stopped at test_axi_to_avalon.sv line 120 +# End time: 07:31:04 on Apr 08,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +``` \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/assets/SYCL_HLS_padding.png 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new file mode 100644 index 0000000000..b3bd286648 Binary files /dev/null and b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/assets/signals-and-interfaces.png differ diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/avst_to_axi_gasket.sv b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/avst_to_axi_gasket.sv deleted file mode 100644 index 74d9835131..0000000000 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/avst_to_axi_gasket.sv +++ /dev/null @@ -1,56 +0,0 @@ -module avalon_to_axi_gasket( - - // clk and resetn don't actually do anything; they are just there to keep - // Platform Designer happy - input logic clk, - input logic resetn, - - // Avalon Streaming Sink Port - output logic avst_sink_ready, - input logic avst_sink_valid, - input logic [95:0] avst_sink_data, - input logic avst_sink_sop, - input logic avst_sink_eop, - input logic [3:0] avst_sink_empty, - - // AXI4-Streaming Transmitter Port - input logic axi_tx_tready, - output logic axi_tx_tvalid, - output logic [63:0] axi_tx_tdata, - output logic axi_tx_tlast, - output logic [7:0] axi_tx_tuser -); - - // pick apart the output from oneAPI IP - logic [9:0] pixel0_r; - logic [9:0] pixel0_g; - logic [9:0] pixel0_b; - - logic [9:0] pixel1_r; - logic [9:0] pixel1_g; - logic [9:0] pixel1_b; - - assign pixel0_r = avst_sink_data[41:32]; - assign pixel0_g = avst_sink_data[25:16]; - assign pixel0_b = avst_sink_data[9:0]; - - assign pixel1_r = avst_sink_data[89:80]; - assign pixel1_g = avst_sink_data[73:64]; - assign pixel1_b = avst_sink_data[57:48]; - - - // map to AXI4-S port - assign avst_sink_ready = axi_tx_tready; - assign axi_tx_tvalid = avst_sink_valid; - assign axi_tx_tdata = {2'b0, pixel1_r, pixel1_g, pixel1_b, 2'b0, pixel0_r, pixel0_g, pixel0_b}; - - // don't support interlaced video, so ignore TUSER[1]. - assign axi_tx_tuser = {6'b0, 1'b0, avst_sink_sop}; - - // eop will go high at the end of each line - assign axi_tx_tlast = avst_sink_eop; - - // ignore empty -endmodule - - diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/axi_to_avst_gasket.sv b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/axi_to_avst_gasket.sv deleted file mode 100644 index c176062392..0000000000 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/axi_to_avst_gasket.sv +++ /dev/null @@ -1,56 +0,0 @@ -module axi_to_avalon_gasket( - - // clk and resetn don't actually do anything; they are just there to keep - // Platform Designer happy - input logic clk, - input logic resetn, - - // AXI4-Streaming Recevier Port - output logic axi_rx_tready, - input logic axi_rx_tvalid, - input logic [63:0] axi_rx_tdata, - input logic axi_rx_tlast, - input logic [7:0] axi_rx_tuser, - - // Avalon Streaming Source Port - input logic avst_source_ready, - output logic avst_source_valid, - output logic [95:0] avst_source_data, - output logic avst_source_sop, - output logic avst_source_eop, - output logic [3:0] avst_source_empty -); - - // pick apart the output from VVP IP - logic [9:0] pixel0_r; - logic [9:0] pixel0_g; - logic [9:0] pixel0_b; - - logic [9:0] pixel1_r; - logic [9:0] pixel1_g; - logic [9:0] pixel1_b; - - assign pixel0_r = axi_rx_tdata[29:20]; - assign pixel0_g = axi_rx_tdata[19:10]; - assign pixel0_b = axi_rx_tdata[9:0]; - - assign pixel1_r = axi_rx_tdata[61:52]; - assign pixel1_g = axi_rx_tdata[51:42]; - assign pixel1_b = axi_rx_tdata[41:32]; - - // map to Avalon streaming port - assign axi_rx_tready = avst_source_ready; - assign avst_source_valid = axi_rx_tvalid; - assign avst_source_data = {6'b0, pixel1_r, 6'b0, pixel1_g, 6'b0, pixel1_b, 6'b0, pixel0_r, 6'b0, pixel0_g, 6'b0, pixel0_b}; - assign avst_source_sop = axi_rx_tuser[0]; - - // eop will go high at the end of each line - assign avst_source_eop = axi_rx_tlast; - - // this signal violates Avalon, but don't worry about it since the oneAPI - // kernel at the other end is designed to ignore `empty`. - assign avst_source_empty = 0; - -endmodule - - diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneAPI_axi4_stream_output_gasket_hw.tcl b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneAPI_axi4_stream_output_gasket_hw.tcl deleted file mode 100644 index e5c41bbce0..0000000000 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneAPI_axi4_stream_output_gasket_hw.tcl +++ /dev/null @@ -1,141 +0,0 @@ -# TCL File Generated by Component Editor 23.2 -# Fri Aug 04 08:03:45 PDT 2023 -# DO NOT MODIFY - - -# -# oneAPI_axi4_stream_output_gasket "oneAPI AXI4-Stream Output Gasket" v0.3 -# Paul White 2023.08.04.08:03:45 -# Allow a oneAPI IP component to output to VVP -# - -# -# request TCL package from ACDS 23.2 -# -package require -exact qsys 23.2 - - -# -# module oneAPI_axi4_stream_output_gasket -# -set_module_property DESCRIPTION "Allow a oneAPI IP component to output to VVP" -set_module_property NAME oneAPI_axi4_stream_output_gasket -set_module_property VERSION 0.3 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property GROUP oneAPI -set_module_property AUTHOR "Paul White" -set_module_property DISPLAY_NAME "oneAPI AXI4-Stream Output Gasket" -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false -set_module_property LOAD_ELABORATION_LIMIT 0 -set_module_property PRE_COMP_MODULE_ENABLED false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_to_axi_gasket -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true -add_fileset_file avst_to_axi_gasket.sv SYSTEM_VERILOG PATH avst_to_axi_gasket.sv TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" -set_interface_property clock IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property clock SV_INTERFACE_TYPE "" -set_interface_property clock SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port clock clk clk Input 1 - - -# -# connection point reset_sink -# -add_interface reset_sink reset end -set_interface_property reset_sink associatedClock clock -set_interface_property reset_sink synchronousEdges DEASSERT -set_interface_property reset_sink ENABLED true -set_interface_property reset_sink EXPORT_OF "" -set_interface_property reset_sink PORT_NAME_MAP "" -set_interface_property reset_sink CMSIS_SVD_VARIABLES "" -set_interface_property reset_sink SVD_ADDRESS_GROUP "" -set_interface_property reset_sink IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property reset_sink SV_INTERFACE_TYPE "" -set_interface_property reset_sink SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port reset_sink resetn reset_n Input 1 - - -# -# connection point avalon_streaming_sink -# -add_interface avalon_streaming_sink avalon_streaming end -set_interface_property avalon_streaming_sink associatedClock clock -set_interface_property avalon_streaming_sink associatedReset reset_sink -set_interface_property avalon_streaming_sink dataBitsPerSymbol 8 -set_interface_property avalon_streaming_sink errorDescriptor "" -set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true -set_interface_property avalon_streaming_sink maxChannel 0 -set_interface_property avalon_streaming_sink readyAllowance 0 -set_interface_property avalon_streaming_sink readyLatency 0 -set_interface_property avalon_streaming_sink ENABLED true -set_interface_property avalon_streaming_sink EXPORT_OF "" -set_interface_property avalon_streaming_sink PORT_NAME_MAP "" -set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES "" -set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP "" -set_interface_property avalon_streaming_sink IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property avalon_streaming_sink SV_INTERFACE_TYPE "" -set_interface_property avalon_streaming_sink SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port avalon_streaming_sink avst_sink_ready ready Output 1 -add_interface_port avalon_streaming_sink avst_sink_valid valid Input 1 -add_interface_port avalon_streaming_sink avst_sink_data data Input 96 -add_interface_port avalon_streaming_sink avst_sink_sop startofpacket Input 1 -add_interface_port avalon_streaming_sink avst_sink_eop endofpacket Input 1 -add_interface_port avalon_streaming_sink avst_sink_empty empty Input 4 - - -# -# connection point axi4stream_master -# -add_interface axi4stream_master axi4stream start -set_interface_property axi4stream_master associatedClock clock -set_interface_property axi4stream_master associatedReset reset_sink -set_interface_property axi4stream_master ENABLED true -set_interface_property axi4stream_master EXPORT_OF "" -set_interface_property axi4stream_master PORT_NAME_MAP "" -set_interface_property axi4stream_master CMSIS_SVD_VARIABLES "" -set_interface_property axi4stream_master SVD_ADDRESS_GROUP "" -set_interface_property axi4stream_master IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property axi4stream_master SV_INTERFACE_TYPE "" -set_interface_property axi4stream_master SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port axi4stream_master axi_tx_tready tready Input 1 -add_interface_port axi4stream_master axi_tx_tvalid tvalid Output 1 -add_interface_port axi4stream_master axi_tx_tdata tdata Output 64 -add_interface_port axi4stream_master axi_tx_tlast tlast Output 1 -add_interface_port axi4stream_master axi_tx_tuser tuser Output 8 - diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneAPI_axi4s_gasket_hw.tcl b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneAPI_axi4s_gasket_hw.tcl deleted file mode 100644 index d75629986a..0000000000 --- a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneAPI_axi4s_gasket_hw.tcl +++ /dev/null @@ -1,141 +0,0 @@ -# TCL File Generated by Component Editor 23.2 -# Fri Aug 04 08:02:03 PDT 2023 -# DO NOT MODIFY - - -# -# oneAPI_axi4s_gasket "oneAPI AXI4-Stream Input Gasket" v0.3 -# Paul White 2023.08.04.08:02:03 -# Allow a oneAPI IP component to communicate with a VVP IP -# - -# -# request TCL package from ACDS 23.2 -# -package require -exact qsys 23.2 - - -# -# module oneAPI_axi4s_gasket -# -set_module_property DESCRIPTION "Allow a oneAPI IP component to communicate with a VVP IP" -set_module_property NAME oneAPI_axi4s_gasket -set_module_property VERSION 0.3 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property GROUP oneAPI -set_module_property AUTHOR "Paul White" -set_module_property DISPLAY_NAME "oneAPI AXI4-Stream Input Gasket" -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false -set_module_property LOAD_ELABORATION_LIMIT 0 -set_module_property PRE_COMP_MODULE_ENABLED false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL axi_to_avalon_gasket -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true -add_fileset_file axi_to_avst_gasket.sv SYSTEM_VERILOG PATH axi_to_avst_gasket.sv TOP_LEVEL_FILE - - -# -# parameters -# - - -# -# display items -# - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock CMSIS_SVD_VARIABLES "" -set_interface_property clock SVD_ADDRESS_GROUP "" -set_interface_property clock IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property clock SV_INTERFACE_TYPE "" -set_interface_property clock SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port clock clk clk Input 1 - - -# -# connection point reset_sink -# -add_interface reset_sink reset end -set_interface_property reset_sink associatedClock clock -set_interface_property reset_sink synchronousEdges DEASSERT -set_interface_property reset_sink ENABLED true -set_interface_property reset_sink EXPORT_OF "" -set_interface_property reset_sink PORT_NAME_MAP "" -set_interface_property reset_sink CMSIS_SVD_VARIABLES "" -set_interface_property reset_sink SVD_ADDRESS_GROUP "" -set_interface_property reset_sink IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property reset_sink SV_INTERFACE_TYPE "" -set_interface_property reset_sink SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port reset_sink resetn reset_n Input 1 - - -# -# connection point axi4stream_slave -# -add_interface axi4stream_slave axi4stream end -set_interface_property axi4stream_slave associatedClock clock -set_interface_property axi4stream_slave associatedReset reset_sink -set_interface_property axi4stream_slave ENABLED true -set_interface_property axi4stream_slave EXPORT_OF "" -set_interface_property axi4stream_slave PORT_NAME_MAP "" -set_interface_property axi4stream_slave CMSIS_SVD_VARIABLES "" -set_interface_property axi4stream_slave SVD_ADDRESS_GROUP "" -set_interface_property axi4stream_slave IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property axi4stream_slave SV_INTERFACE_TYPE "" -set_interface_property axi4stream_slave SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port axi4stream_slave axi_rx_tready tready Output 1 -add_interface_port axi4stream_slave axi_rx_tvalid tvalid Input 1 -add_interface_port axi4stream_slave axi_rx_tdata tdata Input 64 -add_interface_port axi4stream_slave axi_rx_tlast tlast Input 1 -add_interface_port axi4stream_slave axi_rx_tuser tuser Input 8 - - -# -# connection point avalon_streaming_source -# -add_interface avalon_streaming_source avalon_streaming start -set_interface_property avalon_streaming_source associatedClock clock -set_interface_property avalon_streaming_source associatedReset reset_sink -set_interface_property avalon_streaming_source dataBitsPerSymbol 8 -set_interface_property avalon_streaming_source errorDescriptor "" -set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true -set_interface_property avalon_streaming_source maxChannel 0 -set_interface_property avalon_streaming_source readyAllowance 0 -set_interface_property avalon_streaming_source readyLatency 0 -set_interface_property avalon_streaming_source ENABLED true -set_interface_property avalon_streaming_source EXPORT_OF "" -set_interface_property avalon_streaming_source PORT_NAME_MAP "" -set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES "" -set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP "" -set_interface_property avalon_streaming_source IPXACT_REGISTER_MAP_VARIABLES "" -set_interface_property avalon_streaming_source SV_INTERFACE_TYPE "" -set_interface_property avalon_streaming_source SV_INTERFACE_MODPORT_TYPE "" - -add_interface_port avalon_streaming_source avst_source_ready ready Input 1 -add_interface_port avalon_streaming_source avst_source_valid valid Output 1 -add_interface_port avalon_streaming_source avst_source_data data Output 96 -add_interface_port avalon_streaming_source avst_source_sop startofpacket Output 1 -add_interface_port avalon_streaming_source avst_source_eop endofpacket Output 1 -add_interface_port avalon_streaming_source avst_source_empty empty Output 4 - diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_avalon_to_axi_gasket.sv b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_avalon_to_axi_gasket.sv new file mode 100644 index 0000000000..8ac630d6d2 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_avalon_to_axi_gasket.sv @@ -0,0 +1,89 @@ +module oneapi_avalon_to_axi_gasket #( + parameter int PARALLEL_PIXELS = 1, + parameter int BITS_PER_CHANNEL = 8, + parameter int CHANNELS = 3, + + parameter int BITS_PER_CHANNEL_AV = 8, + parameter int BITS_PER_PIXEL_AV = 24, + parameter int BITS_AV = 24, + parameter int EMPTY_BITS = 2, + parameter int BITS_PER_CHANNEL_AXI = 8, + parameter int BITS_PER_PIXEL_AXI = 24, + parameter int BITS_AXI = 24, + parameter int TUSER_BITS = 3, + + // one bit is used for endOfLine, one bit is used for interlaced. The rest + // are filler. + parameter int TUSER_FILL = 1, + + parameter int MASK_OUT = 'hff +) ( + // clk and resetn don't actually do anything; they are just there to keep + // Platform Designer happy + input logic csi_clk, + input logic rsi_reset_n, + + // Avalon Streaming Sink Port + output logic asi_ready, + input logic asi_valid, + input logic [ BITS_AV-1:0] asi_data, + input logic asi_startofpacket, + input logic asi_endofpacket, + input logic [EMPTY_BITS-1:0] asi_empty, + + // AXI4-Streaming Transmitter Port + input logic axm_tready, + output logic axm_tvalid, + output logic [ BITS_AXI-1:0] axm_tdata, + output logic axm_tlast, + output logic [TUSER_BITS-1:0] axm_tuser +); + + // pick apart the output from oneAPI IP + genvar px_id; + genvar channel_id; + generate + + for (px_id = 0; px_id < PARALLEL_PIXELS; px_id++) begin : parallel_pixel_assignment + for (channel_id = 0; channel_id < CHANNELS; channel_id++) begin : parallel_channel_assignment + logic [BITS_PER_CHANNEL_AXI-1:0] pixel_chan; + + localparam LOWER_BIT_AV = px_id * BITS_PER_PIXEL_AV + channel_id * BITS_PER_CHANNEL_AV; + localparam UPPER_BIT_AV = LOWER_BIT_AV + BITS_PER_CHANNEL_AXI - 1; + assign pixel_chan = asi_data[UPPER_BIT_AV:LOWER_BIT_AV]; + + localparam LOWER_BIT_AXI = px_id * BITS_PER_PIXEL_AXI + channel_id * BITS_PER_CHANNEL_AXI; + localparam UPPER_BIT_AXI = LOWER_BIT_AXI + BITS_PER_CHANNEL_AXI - 1; + assign axm_tdata[UPPER_BIT_AXI:LOWER_BIT_AXI] = pixel_chan; + end + end + endgenerate + + + // padding bits for axi + localparam PADDING_BITS_AXI = BITS_PER_PIXEL_AXI - (BITS_PER_CHANNEL_AXI * CHANNELS); + genvar px_id2; + generate + for (px_id2 = 0; px_id2 < PARALLEL_PIXELS; px_id2++) begin : padding_assignment + + localparam LOWER_PADDING_AXI = px_id2 * BITS_PER_PIXEL_AXI + CHANNELS * BITS_PER_CHANNEL_AXI; + localparam UPPER_PADDING_AXI = LOWER_PADDING_AXI + PADDING_BITS_AXI - 1; + if (PADDING_BITS_AXI !== 0) begin + assign axm_tdata[UPPER_PADDING_AXI:LOWER_PADDING_AXI] = 0; + end + end + endgenerate + + // map to AXI4-S port + assign asi_ready = axm_tready; + assign axm_tvalid = asi_valid; + + // don't support interlaced video, so ignore TUSER[1]. + logic [TUSER_FILL-1:0] tuser_fill = 0; + assign axm_tuser = {tuser_fill, 1'b0, asi_startofpacket}; + + // eop will go high at the end of each line + assign axm_tlast = asi_endofpacket; + + // ignore empty +endmodule diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_avalon_to_axi_gasket_hw.tcl b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_avalon_to_axi_gasket_hw.tcl new file mode 100644 index 0000000000..ac6aec72b9 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_avalon_to_axi_gasket_hw.tcl @@ -0,0 +1,353 @@ +# TCL File Generated by Component Editor 23.2 +# Tue Dec 12 06:40:33 PST 2023 +# DO NOT MODIFY + + +# +# oneapi_avalon_to_axi_gasket "oneAPI Avalon Streaming to AXI4 Streaming Gasket" v0.2 +# Intel 2023.12.12.06:40:33 +# Allow a oneAPI IP to connect to an AXI4 Streaming pipeline +# + +# +# request TCL package from ACDS 23.2 +# +package require -exact qsys 23.2 + +proc ld x { + expr {log($x)/[expr log(2)]} +} + +proc elaboration_cb {} { +set param_parallelPixels [get_parameter_value PARALLEL_PIXELS] +set param_bitsPerChannel [get_parameter_value BITS_PER_CHANNEL] +set param_channels [get_parameter_value CHANNELS] + +set bitsPerChannelAv [expr {1 << int(ceil([ld $param_bitsPerChannel]))}] +set bitsPerPixelAv [expr {$bitsPerChannelAv * $param_channels}] +set bitsAv [expr {$bitsPerPixelAv * $param_parallelPixels}] +set emptyBits [expr int(ceil([ld [expr $bitsAv / 8.0]]))] +set bitsPerChannelAxi [expr {$param_bitsPerChannel}] +set bitsPerPixelAxi [expr 8 * int(($param_channels * $bitsPerChannelAxi + 7) / 8.0)] +set bitsAxi [expr {$bitsPerPixelAxi * $param_parallelPixels}] +set tUserBits [expr {int(($bitsAxi + 7) / 8)}] +set tUserFill [expr {$tUserBits - 2}] +set maskOut [expr [expr 1 << [expr $bitsPerChannelAxi]] - 1] + +puts "BITS_PER_CHANNEL_AV $bitsPerChannelAv" +puts "BITS_PER_PIXEL_AV $bitsPerPixelAv" +puts "BITS_AV $bitsAv" +puts "EMPTY_BITS $emptyBits" +puts "BITS_PER_CHANNEL_AXI $bitsPerChannelAxi" +puts "BITS_PER_PIXEL_AXI $bitsPerPixelAxi" +puts "BITS_AXI $bitsAxi" +puts "TUSER_BITS $tUserBits" +puts "TUSER_FILL $tUserFill" +puts [format "MASK_OUT %1x" $maskOut] + +set_parameter_value BITS_PER_CHANNEL_AV $bitsPerChannelAv +set_parameter_value BITS_PER_PIXEL_AV $bitsPerPixelAv +set_parameter_value BITS_AV $bitsAv +set_parameter_value EMPTY_BITS $emptyBits +set_parameter_value BITS_PER_CHANNEL_AXI $bitsPerChannelAxi +set_parameter_value BITS_PER_PIXEL_AXI $bitsPerPixelAxi +set_parameter_value BITS_AXI $bitsAxi +set_parameter_value TUSER_BITS $tUserBits +set_parameter_value TUSER_FILL $tUserFill +set_parameter_value MASK_OUT $maskOut + +set showDerivedParameters [get_parameter_value SHOW_DERIVED_PARAMETERS] +set_parameter_property BITS_PER_CHANNEL_AV VISIBLE $showDerivedParameters +set_parameter_property BITS_PER_PIXEL_AV VISIBLE $showDerivedParameters +set_parameter_property BITS_AV VISIBLE $showDerivedParameters +set_parameter_property EMPTY_BITS VISIBLE $showDerivedParameters +set_parameter_property BITS_PER_CHANNEL_AXI VISIBLE $showDerivedParameters +set_parameter_property BITS_PER_PIXEL_AXI VISIBLE $showDerivedParameters +set_parameter_property BITS_AXI VISIBLE $showDerivedParameters +set_parameter_property TUSER_BITS VISIBLE $showDerivedParameters +set_parameter_property TUSER_FILL VISIBLE $showDerivedParameters +set_parameter_property MASK_OUT VISIBLE $showDerivedParameters + +} + + +# +# module oneapi_avalon_to_axi_gasket +# +set_module_property DESCRIPTION "Allow a oneAPI IP to connect to an AXI4 Streaming pipeline" +set_module_property NAME oneapi_avalon_to_axi_gasket +set_module_property VERSION 0.3 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP oneAPI +set_module_property AUTHOR Intel +set_module_property DISPLAY_NAME "oneAPI Avalon Streaming to AXI4 Streaming Gasket" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false +set_module_property LOAD_ELABORATION_LIMIT 0 +set_module_property PRE_COMP_MODULE_ENABLED false +set_module_property ELABORATION_CALLBACK elaboration_cb + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL oneapi_avalon_to_axi_gasket +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file oneapi_avalon_to_axi_gasket.sv SYSTEM_VERILOG PATH oneapi_avalon_to_axi_gasket.sv TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter PARALLEL_PIXELS INTEGER +set_parameter_property PARALLEL_PIXELS DEFAULT_VALUE 1 +set_parameter_property PARALLEL_PIXELS DISPLAY_NAME "Parallel Pixels" +set_parameter_property PARALLEL_PIXELS WIDTH "" +set_parameter_property PARALLEL_PIXELS UNITS None +set_parameter_property PARALLEL_PIXELS ALLOWED_RANGES 1:8 +set_parameter_property PARALLEL_PIXELS DESCRIPTION "The value of this parameter is the number of pixels that are processed in a single streaming transaction. " +set_parameter_property PARALLEL_PIXELS AFFECTS_GENERATION false +set_parameter_property PARALLEL_PIXELS HDL_PARAMETER true +set_parameter_property PARALLEL_PIXELS EXPORT true +add_parameter CHANNELS INTEGER +set_parameter_property CHANNELS DEFAULT_VALUE 3 +set_parameter_property CHANNELS DISPLAY_NAME "Color Channels" +set_parameter_property CHANNELS WIDTH "" +set_parameter_property CHANNELS UNITS None +set_parameter_property CHANNELS ALLOWED_RANGES 1:8 +set_parameter_property CHANNELS DESCRIPTION "The value of this parameter is the number of color channels in each pixel. For example, RGB pixels would have 3 channels. " +set_parameter_property CHANNELS AFFECTS_GENERATION false +set_parameter_property CHANNELS HDL_PARAMETER true +set_parameter_property CHANNELS EXPORT true +add_parameter BITS_PER_CHANNEL INTEGER +set_parameter_property BITS_PER_CHANNEL DEFAULT_VALUE 8 +set_parameter_property BITS_PER_CHANNEL DISPLAY_NAME "Bits per Channel" +set_parameter_property BITS_PER_CHANNEL WIDTH "" +set_parameter_property BITS_PER_CHANNEL UNITS Bits +set_parameter_property BITS_PER_CHANNEL ALLOWED_RANGES 1:64 +set_parameter_property BITS_PER_CHANNEL DESCRIPTION "The value of this parameter is the number of bits in each color channel on the AXI4-S interface. The number of bits in each channel of the Avalon Streaming interface will be resized to adapt to limitations in the oneAPI compiler. " +set_parameter_property BITS_PER_CHANNEL AFFECTS_GENERATION false +set_parameter_property BITS_PER_CHANNEL HDL_PARAMETER true +set_parameter_property BITS_PER_CHANNEL EXPORT true +add_parameter SHOW_DERIVED_PARAMETERS BOOLEAN false "Display derived parameters in GUI" +set_parameter_property SHOW_DERIVED_PARAMETERS DISPLAY_NAME "Show Derived Parameters" +set_parameter_property SHOW_DERIVED_PARAMETERS AFFECTS_GENERATION false +set_parameter_property SHOW_DERIVED_PARAMETERS DISPLAY_HINT boolean + +add_parameter BITS_PER_CHANNEL_AV INTEGER +set_parameter_property BITS_PER_CHANNEL_AV DERIVED true +set_parameter_property BITS_PER_CHANNEL_AV DEFAULT_VALUE 8 +set_parameter_property BITS_PER_CHANNEL_AV DISPLAY_NAME BITS_PER_CHANNEL_AV +set_parameter_property BITS_PER_CHANNEL_AV WIDTH "" +set_parameter_property BITS_PER_CHANNEL_AV ENABLED false +set_parameter_property BITS_PER_CHANNEL_AV UNITS None +set_parameter_property BITS_PER_CHANNEL_AV ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_CHANNEL_AV DESCRIPTION "" +set_parameter_property BITS_PER_CHANNEL_AV AFFECTS_GENERATION false +set_parameter_property BITS_PER_CHANNEL_AV HDL_PARAMETER true +set_parameter_property BITS_PER_CHANNEL_AV EXPORT true +add_parameter BITS_PER_PIXEL_AV INTEGER +set_parameter_property BITS_PER_PIXEL_AV DERIVED true +set_parameter_property BITS_PER_PIXEL_AV DEFAULT_VALUE 24 +set_parameter_property BITS_PER_PIXEL_AV DISPLAY_NAME BITS_PER_PIXEL_AV +set_parameter_property BITS_PER_PIXEL_AV WIDTH "" +set_parameter_property BITS_PER_PIXEL_AV ENABLED false +set_parameter_property BITS_PER_PIXEL_AV UNITS None +set_parameter_property BITS_PER_PIXEL_AV ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_PIXEL_AV DESCRIPTION "" +set_parameter_property BITS_PER_PIXEL_AV AFFECTS_GENERATION false +set_parameter_property BITS_PER_PIXEL_AV HDL_PARAMETER true +set_parameter_property BITS_PER_PIXEL_AV EXPORT true +add_parameter BITS_AV INTEGER +set_parameter_property BITS_AV DERIVED true +set_parameter_property BITS_AV DEFAULT_VALUE 24 +set_parameter_property BITS_AV DISPLAY_NAME BITS_AV +set_parameter_property BITS_AV WIDTH "" +set_parameter_property BITS_AV ENABLED false +set_parameter_property BITS_AV UNITS None +set_parameter_property BITS_AV ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_AV DESCRIPTION "" +set_parameter_property BITS_AV AFFECTS_GENERATION false +set_parameter_property BITS_AV HDL_PARAMETER true +set_parameter_property BITS_AV EXPORT true +add_parameter EMPTY_BITS INTEGER +set_parameter_property EMPTY_BITS DERIVED true +set_parameter_property EMPTY_BITS DEFAULT_VALUE 2 +set_parameter_property EMPTY_BITS DISPLAY_NAME EMPTY_BITS +set_parameter_property EMPTY_BITS WIDTH "" +set_parameter_property EMPTY_BITS ENABLED false +set_parameter_property EMPTY_BITS UNITS None +set_parameter_property EMPTY_BITS ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property EMPTY_BITS DESCRIPTION "" +set_parameter_property EMPTY_BITS AFFECTS_GENERATION false +set_parameter_property EMPTY_BITS HDL_PARAMETER true +set_parameter_property EMPTY_BITS EXPORT true +add_parameter BITS_PER_CHANNEL_AXI INTEGER +set_parameter_property BITS_PER_CHANNEL_AXI DERIVED true +set_parameter_property BITS_PER_CHANNEL_AXI DEFAULT_VALUE 8 +set_parameter_property BITS_PER_CHANNEL_AXI DISPLAY_NAME BITS_PER_CHANNEL_AXI +set_parameter_property BITS_PER_CHANNEL_AXI WIDTH "" +set_parameter_property BITS_PER_CHANNEL_AXI ENABLED false +set_parameter_property BITS_PER_CHANNEL_AXI UNITS None +set_parameter_property BITS_PER_CHANNEL_AXI ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_CHANNEL_AXI DESCRIPTION "" +set_parameter_property BITS_PER_CHANNEL_AXI AFFECTS_GENERATION false +set_parameter_property BITS_PER_CHANNEL_AXI HDL_PARAMETER true +set_parameter_property BITS_PER_CHANNEL_AXI EXPORT true +add_parameter BITS_PER_PIXEL_AXI INTEGER +set_parameter_property BITS_PER_PIXEL_AXI DERIVED true +set_parameter_property BITS_PER_PIXEL_AXI DEFAULT_VALUE 24 +set_parameter_property BITS_PER_PIXEL_AXI DISPLAY_NAME BITS_PER_PIXEL_AXI +set_parameter_property BITS_PER_PIXEL_AXI WIDTH "" +set_parameter_property BITS_PER_PIXEL_AXI ENABLED false +set_parameter_property BITS_PER_PIXEL_AXI UNITS None +set_parameter_property BITS_PER_PIXEL_AXI ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_PIXEL_AXI DESCRIPTION "" +set_parameter_property BITS_PER_PIXEL_AXI AFFECTS_GENERATION false +set_parameter_property BITS_PER_PIXEL_AXI HDL_PARAMETER true +set_parameter_property BITS_PER_PIXEL_AXI EXPORT true +add_parameter BITS_AXI INTEGER +set_parameter_property BITS_AXI DERIVED true +set_parameter_property BITS_AXI DEFAULT_VALUE 24 +set_parameter_property BITS_AXI DISPLAY_NAME BITS_AXI +set_parameter_property BITS_AXI WIDTH "" +set_parameter_property BITS_AXI ENABLED false +set_parameter_property BITS_AXI UNITS None +set_parameter_property BITS_AXI ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_AXI DESCRIPTION "" +set_parameter_property BITS_AXI AFFECTS_GENERATION false +set_parameter_property BITS_AXI HDL_PARAMETER true +set_parameter_property BITS_AXI EXPORT true +add_parameter TUSER_BITS INTEGER +set_parameter_property TUSER_BITS DERIVED true +set_parameter_property TUSER_BITS DEFAULT_VALUE 3 +set_parameter_property TUSER_BITS DISPLAY_NAME TUSER_BITS +set_parameter_property TUSER_BITS WIDTH "" +set_parameter_property TUSER_BITS ENABLED false +set_parameter_property TUSER_BITS UNITS None +set_parameter_property TUSER_BITS ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property TUSER_BITS DESCRIPTION "" +set_parameter_property TUSER_BITS AFFECTS_GENERATION false +set_parameter_property TUSER_BITS HDL_PARAMETER true +set_parameter_property TUSER_BITS EXPORT true +add_parameter TUSER_FILL INTEGER +set_parameter_property TUSER_FILL DERIVED true +set_parameter_property TUSER_FILL DEFAULT_VALUE 1 +set_parameter_property TUSER_FILL DISPLAY_NAME TUSER_FILL +set_parameter_property TUSER_FILL WIDTH "" +set_parameter_property TUSER_FILL ENABLED false +set_parameter_property TUSER_FILL UNITS None +set_parameter_property TUSER_FILL ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property TUSER_FILL DESCRIPTION "" +set_parameter_property TUSER_FILL AFFECTS_GENERATION false +set_parameter_property TUSER_FILL HDL_PARAMETER true +set_parameter_property TUSER_FILL EXPORT true +add_parameter MASK_OUT INTEGER +set_parameter_property MASK_OUT DERIVED true +set_parameter_property MASK_OUT DEFAULT_VALUE 16777215 +set_parameter_property MASK_OUT DISPLAY_NAME MASK_OUT +set_parameter_property MASK_OUT WIDTH "" +set_parameter_property MASK_OUT ENABLED false +set_parameter_property MASK_OUT UNITS None +set_parameter_property MASK_OUT ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property MASK_OUT DESCRIPTION "" +set_parameter_property MASK_OUT AFFECTS_GENERATION false +set_parameter_property MASK_OUT HDL_PARAMETER true +set_parameter_property MASK_OUT EXPORT true +set_parameter_property MASK_OUT DISPLAY_HINT hexadecimal + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" +set_interface_property clock IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property clock SV_INTERFACE_TYPE "" +set_interface_property clock SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port clock csi_clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" +set_interface_property reset IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property reset SV_INTERFACE_TYPE "" +set_interface_property reset SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port reset rsi_reset_n reset_n Input 1 + + +# +# connection point avalon_streaming_sink +# +add_interface avalon_streaming_sink avalon_streaming end +set_interface_property avalon_streaming_sink associatedClock clock +set_interface_property avalon_streaming_sink associatedReset reset +set_interface_property avalon_streaming_sink dataBitsPerSymbol 8 +set_interface_property avalon_streaming_sink errorDescriptor "" +set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true +set_interface_property avalon_streaming_sink maxChannel 0 +set_interface_property avalon_streaming_sink readyAllowance 0 +set_interface_property avalon_streaming_sink readyLatency 0 +set_interface_property avalon_streaming_sink ENABLED true +set_interface_property avalon_streaming_sink EXPORT_OF "" +set_interface_property avalon_streaming_sink PORT_NAME_MAP "" +set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES "" +set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP "" +set_interface_property avalon_streaming_sink IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property avalon_streaming_sink SV_INTERFACE_TYPE "" +set_interface_property avalon_streaming_sink SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port avalon_streaming_sink asi_ready ready Output 1 +add_interface_port avalon_streaming_sink asi_valid valid Input 1 +add_interface_port avalon_streaming_sink asi_data data Input "((BITS_AV - 1)) - (0) + 1" +add_interface_port avalon_streaming_sink asi_startofpacket startofpacket Input 1 +add_interface_port avalon_streaming_sink asi_endofpacket endofpacket Input 1 +add_interface_port avalon_streaming_sink asi_empty empty Input "((EMPTY_BITS - 1)) - (0) + 1" + + +# +# connection point axi4stream_transmitter +# +add_interface axi4stream_transmitter axi4stream start +set_interface_property axi4stream_transmitter associatedClock clock +set_interface_property axi4stream_transmitter associatedReset reset +set_interface_property axi4stream_transmitter ENABLED true +set_interface_property axi4stream_transmitter EXPORT_OF "" +set_interface_property axi4stream_transmitter PORT_NAME_MAP "" +set_interface_property axi4stream_transmitter CMSIS_SVD_VARIABLES "" +set_interface_property axi4stream_transmitter SVD_ADDRESS_GROUP "" +set_interface_property axi4stream_transmitter IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property axi4stream_transmitter SV_INTERFACE_TYPE "" +set_interface_property axi4stream_transmitter SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port axi4stream_transmitter axm_tready tready Input 1 +add_interface_port axi4stream_transmitter axm_tvalid tvalid Output 1 +add_interface_port axi4stream_transmitter axm_tdata tdata Output "((BITS_AXI - 1)) - (0) + 1" +add_interface_port axi4stream_transmitter axm_tlast tlast Output 1 +add_interface_port axi4stream_transmitter axm_tuser tuser Output "((TUSER_BITS - 1)) - (0) + 1" diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_axi_to_avalon_gasket.sv b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_axi_to_avalon_gasket.sv new file mode 100644 index 0000000000..f06982deff --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_axi_to_avalon_gasket.sv @@ -0,0 +1,74 @@ +module oneapi_axi_to_avalon_gasket #( + parameter int PARALLEL_PIXELS = 1, + parameter int BITS_PER_CHANNEL = 8, + parameter int CHANNELS = 3, + + parameter int BITS_PER_CHANNEL_AV = 8, + parameter int BITS_PER_PIXEL_AV = 24, + parameter int BITS_AV = 24, + parameter int EMPTY_BITS = 2, + parameter int BITS_PER_CHANNEL_AXI = 8, + parameter int BITS_PER_PIXEL_AXI = 24, + parameter int BITS_AXI = 24, + parameter int TUSER_BITS = 3, + + // one bit is used for endOfLine, one bit is used for interlaced. The rest + // are filler. + parameter int TUSER_FILL = 1, + + parameter int MASK_OUT = 'hff +) ( + // clk and resetn don't actually do anything; they are just there to keep + // Platform Designer happy + input logic csi_clk, + input logic rsi_reset_n, + + // AXI4-Streaming Receiver Port + output logic axs_tready, + input logic axs_tvalid, + input logic [ BITS_AXI-1:0] axs_tdata, + input logic axs_tlast, + input logic [TUSER_BITS-1:0] axs_tuser, + + // Avalon Streaming Source Port + input logic aso_ready, + output logic aso_valid, + output logic [ BITS_AV-1:0] aso_data, + output logic aso_startofpacket, + output logic aso_endofpacket, + output logic [EMPTY_BITS-1:0] aso_empty +); + + // pick apart the output from VVP IP + genvar px_id; + genvar channel_id; + generate + + for (px_id = 0; px_id < PARALLEL_PIXELS; px_id++) begin : parallel_pixel_assignment + for (channel_id = 0; channel_id < CHANNELS; channel_id++) begin : parallel_channel_assignment + logic [BITS_PER_CHANNEL_AV-1:0] pixel_chan; + + localparam LOWER_BIT_AXI = px_id * BITS_PER_PIXEL_AXI + channel_id * BITS_PER_CHANNEL_AXI; + localparam UPPER_BIT_AXI = LOWER_BIT_AXI + BITS_PER_CHANNEL_AXI - 1; + assign pixel_chan = axs_tdata[UPPER_BIT_AXI:LOWER_BIT_AXI] & MASK_OUT; + + localparam LOWER_BIT_AV = px_id * BITS_PER_PIXEL_AV + channel_id * BITS_PER_CHANNEL_AV; + localparam UPPER_BIT_AV = LOWER_BIT_AV + BITS_PER_CHANNEL_AV - 1; + assign aso_data[UPPER_BIT_AV:LOWER_BIT_AV] = pixel_chan; + end + end + + endgenerate + + // map to Avalon streaming port + assign axs_tready = aso_ready; + assign aso_valid = axs_tvalid; + assign aso_startofpacket = axs_tuser[0]; + + // eop will go high at the end of each line + assign aso_endofpacket = axs_tlast; + + // this signal violates Avalon, but don't worry about it since the oneAPI + // kernel at the other end is designed to ignore `empty`. + assign aso_empty = 0; +endmodule diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_axi_to_avalon_gasket_hw.tcl b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_axi_to_avalon_gasket_hw.tcl new file mode 100644 index 0000000000..a484652ad7 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/oneapi_axi_to_avalon_gasket_hw.tcl @@ -0,0 +1,354 @@ +# TCL File Generated by Component Editor 23.2 +# Tue Dec 12 06:40:33 PST 2023 +# DO NOT MODIFY + + +# +# oneapi_axi_to_avalon_gasket "oneAPI AXI4 Streaming to Avalon Streaming Gasket" v0.2 +# Intel 2023.12.12.06:40:33 +# Allow an AXI4 Streaming pipeline to connect to a oneAPI IP +# + +# +# request TCL package from ACDS 23.2 +# +package require -exact qsys 23.2 + +proc ld x { + expr {log($x)/[expr log(2)]} +} + +proc elaboration_cb {} { +set param_parallelPixels [get_parameter_value PARALLEL_PIXELS] +set param_bitsPerChannel [get_parameter_value BITS_PER_CHANNEL] +set param_channels [get_parameter_value CHANNELS] + +set bitsPerChannelAv [expr {1 << int(ceil([ld $param_bitsPerChannel]))}] +set bitsPerPixelAv [expr {$bitsPerChannelAv * $param_channels}] +set bitsAv [expr {$bitsPerPixelAv * $param_parallelPixels}] +set emptyBits [expr int(ceil([ld [expr $bitsAv / 8.0]]))] +set bitsPerChannelAxi [expr {$param_bitsPerChannel}] +set bitsPerPixelAxi [expr 8 * int(($param_channels * $bitsPerChannelAxi + 7) / 8.0)] +set bitsAxi [expr {$bitsPerPixelAxi * $param_parallelPixels}] +set tUserBits [expr {int(($bitsAxi + 7) / 8)}] +set tUserFill [expr {$tUserBits - 2}] +set maskOut [expr [expr 1 << [expr $bitsPerChannelAxi]] - 1] + +puts "BITS_PER_CHANNEL_AV $bitsPerChannelAv" +puts "BITS_PER_PIXEL_AV $bitsPerPixelAv" +puts "BITS_AV $bitsAv" +puts "EMPTY_BITS $emptyBits" +puts "BITS_PER_CHANNEL_AXI $bitsPerChannelAxi" +puts "BITS_PER_PIXEL_AXI $bitsPerPixelAxi" +puts "BITS_AXI $bitsAxi" +puts "TUSER_BITS $tUserBits" +puts "TUSER_FILL $tUserFill" +puts [format "MASK_OUT %1x" $maskOut] + +set_parameter_value BITS_PER_CHANNEL_AV $bitsPerChannelAv +set_parameter_value BITS_PER_PIXEL_AV $bitsPerPixelAv +set_parameter_value BITS_AV $bitsAv +set_parameter_value EMPTY_BITS $emptyBits +set_parameter_value BITS_PER_CHANNEL_AXI $bitsPerChannelAxi +set_parameter_value BITS_PER_PIXEL_AXI $bitsPerPixelAxi +set_parameter_value BITS_AXI $bitsAxi +set_parameter_value TUSER_BITS $tUserBits +set_parameter_value TUSER_FILL $tUserFill +set_parameter_value MASK_OUT $maskOut + +set showDerivedParameters [get_parameter_value SHOW_DERIVED_PARAMETERS] +set_parameter_property BITS_PER_CHANNEL_AV VISIBLE $showDerivedParameters +set_parameter_property BITS_PER_PIXEL_AV VISIBLE $showDerivedParameters +set_parameter_property BITS_AV VISIBLE $showDerivedParameters +set_parameter_property EMPTY_BITS VISIBLE $showDerivedParameters +set_parameter_property BITS_PER_CHANNEL_AXI VISIBLE $showDerivedParameters +set_parameter_property BITS_PER_PIXEL_AXI VISIBLE $showDerivedParameters +set_parameter_property BITS_AXI VISIBLE $showDerivedParameters +set_parameter_property TUSER_BITS VISIBLE $showDerivedParameters +set_parameter_property TUSER_FILL VISIBLE $showDerivedParameters +set_parameter_property MASK_OUT VISIBLE $showDerivedParameters + +} + + +# +# module oneapi_axi_to_avalon_gasket +# +set_module_property DESCRIPTION "Allow an AXI4 Streaming pipeline to connect to a oneAPI IP" +set_module_property NAME oneapi_axi_to_avalon_gasket +set_module_property VERSION 0.3 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP oneAPI +set_module_property AUTHOR Intel +set_module_property DISPLAY_NAME "oneAPI AXI4 Streaming to Avalon Streaming Gasket" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false +set_module_property LOAD_ELABORATION_LIMIT 0 +set_module_property PRE_COMP_MODULE_ENABLED false +set_module_property ELABORATION_CALLBACK elaboration_cb + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL oneapi_axi_to_avalon_gasket +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file oneapi_axi_to_avalon_gasket.sv SYSTEM_VERILOG PATH oneapi_axi_to_avalon_gasket.sv TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter PARALLEL_PIXELS INTEGER +set_parameter_property PARALLEL_PIXELS DEFAULT_VALUE 1 +set_parameter_property PARALLEL_PIXELS DISPLAY_NAME "Parallel Pixels" +set_parameter_property PARALLEL_PIXELS WIDTH "" +set_parameter_property PARALLEL_PIXELS UNITS None +set_parameter_property PARALLEL_PIXELS ALLOWED_RANGES 1:8 +set_parameter_property PARALLEL_PIXELS DESCRIPTION "The value of this parameter is the number of pixels that are processed in a single streaming transaction. " +set_parameter_property PARALLEL_PIXELS AFFECTS_GENERATION false +set_parameter_property PARALLEL_PIXELS HDL_PARAMETER true +set_parameter_property PARALLEL_PIXELS EXPORT true +add_parameter CHANNELS INTEGER +set_parameter_property CHANNELS DEFAULT_VALUE 3 +set_parameter_property CHANNELS DISPLAY_NAME "Color Channels" +set_parameter_property CHANNELS WIDTH "" +set_parameter_property CHANNELS UNITS None +set_parameter_property CHANNELS ALLOWED_RANGES 1:8 +set_parameter_property CHANNELS DESCRIPTION "The value of this parameter is the number of color channels in each pixel. For example, RGB pixels would have 3 channels. " +set_parameter_property CHANNELS AFFECTS_GENERATION false +set_parameter_property CHANNELS HDL_PARAMETER true +set_parameter_property CHANNELS EXPORT true +add_parameter BITS_PER_CHANNEL INTEGER +set_parameter_property BITS_PER_CHANNEL DEFAULT_VALUE 8 +set_parameter_property BITS_PER_CHANNEL DISPLAY_NAME "Bits per Channel" +set_parameter_property BITS_PER_CHANNEL WIDTH "" +set_parameter_property BITS_PER_CHANNEL UNITS Bits +set_parameter_property BITS_PER_CHANNEL ALLOWED_RANGES 1:64 +set_parameter_property BITS_PER_CHANNEL DESCRIPTION "The value of this parameter is the number of bits in each color channel on the AXI4-S interface. The number of bits in each channel of the Avalon Streaming interface will be resized to adapt to limitations in the oneAPI compiler. " +set_parameter_property BITS_PER_CHANNEL AFFECTS_GENERATION false +set_parameter_property BITS_PER_CHANNEL HDL_PARAMETER true +set_parameter_property BITS_PER_CHANNEL EXPORT true +add_parameter SHOW_DERIVED_PARAMETERS BOOLEAN false "Display derived parameters in GUI" +set_parameter_property SHOW_DERIVED_PARAMETERS DISPLAY_NAME "Show Derived Parameters" +set_parameter_property SHOW_DERIVED_PARAMETERS AFFECTS_GENERATION false +set_parameter_property SHOW_DERIVED_PARAMETERS DISPLAY_HINT boolean + +add_parameter BITS_PER_CHANNEL_AV INTEGER +set_parameter_property BITS_PER_CHANNEL_AV DERIVED true +set_parameter_property BITS_PER_CHANNEL_AV DEFAULT_VALUE 8 +set_parameter_property BITS_PER_CHANNEL_AV DISPLAY_NAME BITS_PER_CHANNEL_AV +set_parameter_property BITS_PER_CHANNEL_AV WIDTH "" +set_parameter_property BITS_PER_CHANNEL_AV ENABLED false +set_parameter_property BITS_PER_CHANNEL_AV UNITS None +set_parameter_property BITS_PER_CHANNEL_AV ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_CHANNEL_AV DESCRIPTION "" +set_parameter_property BITS_PER_CHANNEL_AV AFFECTS_GENERATION false +set_parameter_property BITS_PER_CHANNEL_AV HDL_PARAMETER true +set_parameter_property BITS_PER_CHANNEL_AV EXPORT true +add_parameter BITS_PER_PIXEL_AV INTEGER +set_parameter_property BITS_PER_PIXEL_AV DERIVED true +set_parameter_property BITS_PER_PIXEL_AV DEFAULT_VALUE 24 +set_parameter_property BITS_PER_PIXEL_AV DISPLAY_NAME BITS_PER_PIXEL_AV +set_parameter_property BITS_PER_PIXEL_AV WIDTH "" +set_parameter_property BITS_PER_PIXEL_AV ENABLED false +set_parameter_property BITS_PER_PIXEL_AV UNITS None +set_parameter_property BITS_PER_PIXEL_AV ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_PIXEL_AV DESCRIPTION "" +set_parameter_property BITS_PER_PIXEL_AV AFFECTS_GENERATION false +set_parameter_property BITS_PER_PIXEL_AV HDL_PARAMETER true +set_parameter_property BITS_PER_PIXEL_AV EXPORT true +add_parameter BITS_AV INTEGER +set_parameter_property BITS_AV DERIVED true +set_parameter_property BITS_AV DEFAULT_VALUE 24 +set_parameter_property BITS_AV DISPLAY_NAME BITS_AV +set_parameter_property BITS_AV WIDTH "" +set_parameter_property BITS_AV ENABLED false +set_parameter_property BITS_AV UNITS None +set_parameter_property BITS_AV ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_AV DESCRIPTION "" +set_parameter_property BITS_AV AFFECTS_GENERATION false +set_parameter_property BITS_AV HDL_PARAMETER true +set_parameter_property BITS_AV EXPORT true +add_parameter EMPTY_BITS INTEGER +set_parameter_property EMPTY_BITS DERIVED true +set_parameter_property EMPTY_BITS DEFAULT_VALUE 2 +set_parameter_property EMPTY_BITS DISPLAY_NAME EMPTY_BITS +set_parameter_property EMPTY_BITS WIDTH "" +set_parameter_property EMPTY_BITS ENABLED false +set_parameter_property EMPTY_BITS UNITS None +set_parameter_property EMPTY_BITS ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property EMPTY_BITS DESCRIPTION "" +set_parameter_property EMPTY_BITS AFFECTS_GENERATION false +set_parameter_property EMPTY_BITS HDL_PARAMETER true +set_parameter_property EMPTY_BITS EXPORT true +add_parameter BITS_PER_CHANNEL_AXI INTEGER +set_parameter_property BITS_PER_CHANNEL_AXI DERIVED true +set_parameter_property BITS_PER_CHANNEL_AXI DEFAULT_VALUE 8 +set_parameter_property BITS_PER_CHANNEL_AXI DISPLAY_NAME BITS_PER_CHANNEL_AXI +set_parameter_property BITS_PER_CHANNEL_AXI WIDTH "" +set_parameter_property BITS_PER_CHANNEL_AXI ENABLED false +set_parameter_property BITS_PER_CHANNEL_AXI UNITS None +set_parameter_property BITS_PER_CHANNEL_AXI ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_CHANNEL_AXI DESCRIPTION "" +set_parameter_property BITS_PER_CHANNEL_AXI AFFECTS_GENERATION false +set_parameter_property BITS_PER_CHANNEL_AXI HDL_PARAMETER true +set_parameter_property BITS_PER_CHANNEL_AXI EXPORT true +add_parameter BITS_PER_PIXEL_AXI INTEGER +set_parameter_property BITS_PER_PIXEL_AXI DERIVED true +set_parameter_property BITS_PER_PIXEL_AXI DEFAULT_VALUE 24 +set_parameter_property BITS_PER_PIXEL_AXI DISPLAY_NAME BITS_PER_PIXEL_AXI +set_parameter_property BITS_PER_PIXEL_AXI WIDTH "" +set_parameter_property BITS_PER_PIXEL_AXI ENABLED false +set_parameter_property BITS_PER_PIXEL_AXI UNITS None +set_parameter_property BITS_PER_PIXEL_AXI ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_PER_PIXEL_AXI DESCRIPTION "" +set_parameter_property BITS_PER_PIXEL_AXI AFFECTS_GENERATION false +set_parameter_property BITS_PER_PIXEL_AXI HDL_PARAMETER true +set_parameter_property BITS_PER_PIXEL_AXI EXPORT true +add_parameter BITS_AXI INTEGER +set_parameter_property BITS_AXI DERIVED true +set_parameter_property BITS_AXI DEFAULT_VALUE 24 +set_parameter_property BITS_AXI DISPLAY_NAME BITS_AXI +set_parameter_property BITS_AXI WIDTH "" +set_parameter_property BITS_AXI ENABLED false +set_parameter_property BITS_AXI UNITS None +set_parameter_property BITS_AXI ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property BITS_AXI DESCRIPTION "" +set_parameter_property BITS_AXI AFFECTS_GENERATION false +set_parameter_property BITS_AXI HDL_PARAMETER true +set_parameter_property BITS_AXI EXPORT true +add_parameter TUSER_BITS INTEGER +set_parameter_property TUSER_BITS DERIVED true +set_parameter_property TUSER_BITS DEFAULT_VALUE 3 +set_parameter_property TUSER_BITS DISPLAY_NAME TUSER_BITS +set_parameter_property TUSER_BITS WIDTH "" +set_parameter_property TUSER_BITS ENABLED false +set_parameter_property TUSER_BITS UNITS None +set_parameter_property TUSER_BITS ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property TUSER_BITS DESCRIPTION "" +set_parameter_property TUSER_BITS AFFECTS_GENERATION false +set_parameter_property TUSER_BITS HDL_PARAMETER true +set_parameter_property TUSER_BITS EXPORT true +add_parameter TUSER_FILL INTEGER +set_parameter_property TUSER_FILL DERIVED true +set_parameter_property TUSER_FILL DEFAULT_VALUE 1 +set_parameter_property TUSER_FILL DISPLAY_NAME TUSER_FILL +set_parameter_property TUSER_FILL WIDTH "" +set_parameter_property TUSER_FILL ENABLED false +set_parameter_property TUSER_FILL UNITS None +set_parameter_property TUSER_FILL ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property TUSER_FILL DESCRIPTION "" +set_parameter_property TUSER_FILL AFFECTS_GENERATION false +set_parameter_property TUSER_FILL HDL_PARAMETER true +set_parameter_property TUSER_FILL EXPORT true +add_parameter MASK_OUT INTEGER +set_parameter_property MASK_OUT DERIVED true +set_parameter_property MASK_OUT DEFAULT_VALUE 16777215 +set_parameter_property MASK_OUT DISPLAY_NAME MASK_OUT +set_parameter_property MASK_OUT WIDTH "" +set_parameter_property MASK_OUT ENABLED false +set_parameter_property MASK_OUT UNITS None +set_parameter_property MASK_OUT ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property MASK_OUT DESCRIPTION "" +set_parameter_property MASK_OUT AFFECTS_GENERATION false +set_parameter_property MASK_OUT HDL_PARAMETER true +set_parameter_property MASK_OUT EXPORT true +set_parameter_property MASK_OUT DISPLAY_HINT hexadecimal + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" +set_interface_property clock IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property clock SV_INTERFACE_TYPE "" +set_interface_property clock SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port clock csi_clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" +set_interface_property reset IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property reset SV_INTERFACE_TYPE "" +set_interface_property reset SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port reset rsi_reset_n reset_n Input 1 + + +# +# connection point axi4stream_receiver +# +add_interface axi4stream_receiver axi4stream end +set_interface_property axi4stream_receiver associatedClock clock +set_interface_property axi4stream_receiver associatedReset reset +set_interface_property axi4stream_receiver ENABLED true +set_interface_property axi4stream_receiver EXPORT_OF "" +set_interface_property axi4stream_receiver PORT_NAME_MAP "" +set_interface_property axi4stream_receiver CMSIS_SVD_VARIABLES "" +set_interface_property axi4stream_receiver SVD_ADDRESS_GROUP "" +set_interface_property axi4stream_receiver IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property axi4stream_receiver SV_INTERFACE_TYPE "" +set_interface_property axi4stream_receiver SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port axi4stream_receiver axs_tready tready Output 1 +add_interface_port axi4stream_receiver axs_tvalid tvalid Input 1 +add_interface_port axi4stream_receiver axs_tdata tdata Input "((BITS_AXI - 1)) - (0) + 1" +add_interface_port axi4stream_receiver axs_tlast tlast Input 1 +add_interface_port axi4stream_receiver axs_tuser tuser Input "((TUSER_BITS - 1)) - (0) + 1" + + +# +# connection point avalon_streaming_source +# +add_interface avalon_streaming_source avalon_streaming start +set_interface_property avalon_streaming_source associatedClock clock +set_interface_property avalon_streaming_source associatedReset reset +set_interface_property avalon_streaming_source dataBitsPerSymbol 8 +set_interface_property avalon_streaming_source errorDescriptor "" +set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true +set_interface_property avalon_streaming_source maxChannel 0 +set_interface_property avalon_streaming_source readyAllowance 0 +set_interface_property avalon_streaming_source readyLatency 0 +set_interface_property avalon_streaming_source ENABLED true +set_interface_property avalon_streaming_source EXPORT_OF "" +set_interface_property avalon_streaming_source PORT_NAME_MAP "" +set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES "" +set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP "" +set_interface_property avalon_streaming_source IPXACT_REGISTER_MAP_VARIABLES "" +set_interface_property avalon_streaming_source SV_INTERFACE_TYPE "" +set_interface_property avalon_streaming_source SV_INTERFACE_MODPORT_TYPE "" + +add_interface_port avalon_streaming_source aso_ready ready Input 1 +add_interface_port avalon_streaming_source aso_valid valid Output 1 +add_interface_port avalon_streaming_source aso_data data Output "((BITS_AV - 1)) - (0) + 1" +add_interface_port avalon_streaming_source aso_startofpacket startofpacket Output 1 +add_interface_port avalon_streaming_source aso_endofpacket endofpacket Output 1 +add_interface_port avalon_streaming_source aso_empty empty Output "((EMPTY_BITS - 1)) - (0) + 1" + diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_avalon_to_axi.do b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_avalon_to_axi.do new file mode 100644 index 0000000000..596587b496 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_avalon_to_axi.do @@ -0,0 +1,6 @@ +vlib work +vlog -reportprogress 300 -work work oneapi_avalon_to_axi_gasket.sv +vlog -reportprogress 300 -work work test_avalon_to_axi.sv +vsim work.oneapi_avalon_to_axi_gasket work.test_avalon_to_axi +run -all +exit \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_avalon_to_axi.sv b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_avalon_to_axi.sv new file mode 100644 index 0000000000..d539d2575c --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_avalon_to_axi.sv @@ -0,0 +1,123 @@ +module test_avalon_to_axi; + + `define PARALLEL_PIXELS 2 + `define BITS_PER_CHANNEL 10 + `define CHANNELS 3 + + `define BITS_PER_CHANNEL_AV (1 << $clog2(`BITS_PER_CHANNEL)) + `define BITS_PER_PIXEL_AV (`BITS_PER_CHANNEL_AV * `CHANNELS) + `define BITS_AV (`BITS_PER_PIXEL_AV * `PARALLEL_PIXELS) + `define EMPTY_BITS ($clog2(`BITS_AV / 8)) + `define BITS_PER_CHANNEL_AXI (`BITS_PER_CHANNEL) + `define BITS_PER_PIXEL_AXI (8 * ((`CHANNELS * `BITS_PER_CHANNEL_AXI + 7) / 8)) + `define BITS_AXI (`BITS_PER_PIXEL_AXI * `PARALLEL_PIXELS) + `define TUSER_BITS ((`BITS_AXI + 7)/ 8) + `define TUSER_FILL (`TUSER_BITS - 2) + `define MASK_OUT ((1 << `BITS_PER_CHANNEL_AXI) - 1) + + + // clk and resetn don't actually do anything; they are just there to keep + // Platform Designer happy + logic cin; + logic reset_n; + + // Avalon Streaming Sink Port + logic asi_ready; + logic asi_valid; + logic [ `BITS_AV-1:0] asi_data; + logic asi_startofpacket; + logic asi_endofpacket; + logic [`EMPTY_BITS-1:0] asi_empty; + + // AXI4 Transmitter + logic axm_tready; + logic axm_tvalid; + logic [ `BITS_AXI-1:0] axm_tdata; + logic axm_tlast; + logic [`TUSER_BITS-1:0] axm_tuser; + + // Instantiate the Device Under Test (DUT) + oneapi_avalon_to_axi_gasket #( + `PARALLEL_PIXELS , + `BITS_PER_CHANNEL , + `CHANNELS , + `BITS_PER_CHANNEL_AV , + `BITS_PER_PIXEL_AV , + `BITS_AV , + `EMPTY_BITS , + `BITS_PER_CHANNEL_AXI, + `BITS_PER_PIXEL_AXI , + `BITS_AXI , + `TUSER_BITS , + `TUSER_FILL , + `MASK_OUT ) + avalon_to_axi ( + .csi_clk(cin), + .rsi_reset_n(reset_n), + + // Avalon Streaming Sink Port + .asi_ready(asi_ready), + .asi_valid(asi_valid), + .asi_data(asi_data), + .asi_startofpacket(asi_startofpacket), + .asi_endofpacket(asi_endofpacket), + .asi_empty(asi_empty), + + // AXI4-Streaming Transmitter Port + .axm_tready(axm_tready), + .axm_tvalid(axm_tvalid), + .axm_tdata (axm_tdata), + .axm_tlast (axm_tlast), + .axm_tuser (axm_tuser) + ); + + initial begin + cin = 0; + reset_n = 0; + while (1) begin + #5; + cin = ~cin; + end + end + + initial begin + $display("PARALLEL_PIXELS = %d", `PARALLEL_PIXELS); + $display("BITS_PER_CHANNEL = %d", `BITS_PER_CHANNEL); + $display("CHANNELS = %d", `CHANNELS); + $display("BITS_PER_CHANNEL_AV = %d", `BITS_PER_CHANNEL_AV); + $display("BITS_PER_PIXEL_AV = %d", `BITS_PER_PIXEL_AV); + $display("BITS_AV = %d", `BITS_AV); + $display("EMPTY_BITS = %d", `EMPTY_BITS); + $display("BITS_PER_CHANNEL_AXI = %d", `BITS_PER_CHANNEL_AXI); + $display("BITS_PER_PIXEL_AXI = %d", `BITS_PER_PIXEL_AXI); + $display("BITS_AXI = %d", `BITS_AXI); + $display("TUSER_BITS = %d", `TUSER_BITS); + $display("TUSER_FILL = %d", `TUSER_FILL); + $display("MASK_OUT = %x", `MASK_OUT); + + $monitor( + "cin 0b%b | reset_n 0b%b | axm_tready 0b%b | axm_tvalid 0b%b | axm_tdata 0x%h | axm_tlast 0x%h | axm_tuser 0x%h | asi_ready 0b%b | asi_valid 0b%b | asi_data 0x%h | asi_sop 0b%b | asi_endofpacket 0b%b | asi_empty 0b%b", + cin, reset_n, axm_tready, axm_tvalid, axm_tdata, axm_tlast, axm_tuser, asi_ready, + asi_valid, asi_data, asi_startofpacket, asi_endofpacket, asi_empty); + end + + logic [`BITS_PER_PIXEL_AV-1:0] pixel1_asi; + logic [`BITS_PER_PIXEL_AV-1:0] pixel2_asi; + + initial begin + @(negedge cin); + reset_n = 1'b1; + @(negedge cin); + asi_valid <= 1; + assign pixel1_asi = {16'h13, 16'h12, 16'h11}; + assign pixel2_asi = {16'h23, 16'h22, 16'h21}; + asi_data <= {pixel2_asi, pixel1_asi}; + asi_endofpacket <= 0; + asi_startofpacket <= 0; + + axm_tready <= 1; + @(negedge cin); + $stop; + end + +endmodule diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_axi_to_avalon.do b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_axi_to_avalon.do new file mode 100644 index 0000000000..377d054a0f --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_axi_to_avalon.do @@ -0,0 +1,6 @@ +vlib work +vlog -reportprogress 300 -work work oneapi_axi_to_avalon_gasket.sv +vlog -reportprogress 300 -work work test_axi_to_avalon.sv +vsim work.oneapi_axi_to_avalon_gasket work.test_axi_to_avalon +run -all +exit \ No newline at end of file diff --git a/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_axi_to_avalon.sv b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_axi_to_avalon.sv new file mode 100644 index 0000000000..4ac02e6912 --- /dev/null +++ b/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/convolution2d/quartus_project_files/non_acds_ip/oneAPI_streaming_gasket/test_axi_to_avalon.sv @@ -0,0 +1,123 @@ +module test_axi_to_avalon; + + `define PARALLEL_PIXELS 2 + `define BITS_PER_CHANNEL 10 + `define CHANNELS 3 + + `define BITS_PER_CHANNEL_AV (1 << $clog2(`BITS_PER_CHANNEL)) + `define BITS_PER_PIXEL_AV (`BITS_PER_CHANNEL_AV * `CHANNELS) + `define BITS_AV (`BITS_PER_PIXEL_AV * `PARALLEL_PIXELS) + `define EMPTY_BITS ($clog2(`BITS_AV / 8)) + `define BITS_PER_CHANNEL_AXI (`BITS_PER_CHANNEL) + `define BITS_PER_PIXEL_AXI (8 * ((`CHANNELS * `BITS_PER_CHANNEL_AXI + 7) / 8)) + `define BITS_AXI (`BITS_PER_PIXEL_AXI * `PARALLEL_PIXELS) + `define TUSER_BITS ((`BITS_AXI + 7)/ 8) + `define TUSER_FILL (`TUSER_BITS - 2) + `define MASK_OUT ((1 << `BITS_PER_CHANNEL_AXI) - 1) + + + // clk and resetn don't actually do anything; they are just there to keep + // Platform Designer happy + logic cin; + logic reset_n; + + // AXI4 Receiver + logic axs_tready; + logic axs_tvalid; + logic [ `BITS_AXI-1:0] axs_tdata; + logic axs_tlast; + logic [`TUSER_BITS-1:0] axs_tuser; + + // Avalon Streaming Source Port + logic aso_ready; + logic aso_valid; + logic [ `BITS_AV-1:0] aso_data; + logic aso_startofpacket; + logic aso_endofpacket; + logic [`EMPTY_BITS-1:0] aso_empty; + + // Instantiate the Device Under Test (DUT) + oneapi_axi_to_avalon_gasket #( + `PARALLEL_PIXELS , + `BITS_PER_CHANNEL , + `CHANNELS , + `BITS_PER_CHANNEL_AV , + `BITS_PER_PIXEL_AV , + `BITS_AV , + `EMPTY_BITS , + `BITS_PER_CHANNEL_AXI, + `BITS_PER_PIXEL_AXI , + `BITS_AXI , + `TUSER_BITS , + `TUSER_FILL , + `MASK_OUT ) + axi_to_avalon ( + .csi_clk(cin), + .rsi_reset_n(reset_n), + + // AXI4-Streaming Receiver Port + .axs_tready(axs_tready), + .axs_tvalid(axs_tvalid), + .axs_tdata (axs_tdata), + .axs_tlast (axs_tlast), + .axs_tuser (axs_tuser), + + // Avalon Streaming Source Port + .aso_ready(aso_ready), + .aso_valid(aso_valid), + .aso_data(aso_data), + .aso_startofpacket(aso_startofpacket), + .aso_endofpacket(aso_endofpacket), + .aso_empty(aso_empty) + ); + + initial begin + cin = 0; + reset_n = 0; + while (1) begin + #5; + cin = ~cin; + end + end + + initial begin + $display("PARALLEL_PIXELS = %d", `PARALLEL_PIXELS); + $display("BITS_PER_CHANNEL = %d", `BITS_PER_CHANNEL); + $display("CHANNELS = %d", `CHANNELS); + $display("BITS_PER_CHANNEL_AV = %d", `BITS_PER_CHANNEL_AV); + $display("BITS_PER_PIXEL_AV = %d", `BITS_PER_PIXEL_AV); + $display("BITS_AV = %d", `BITS_AV); + $display("EMPTY_BITS = %d", `EMPTY_BITS); + $display("BITS_PER_CHANNEL_AXI = %d", `BITS_PER_CHANNEL_AXI); + $display("BITS_PER_PIXEL_AXI = %d", `BITS_PER_PIXEL_AXI); + $display("BITS_AXI = %d", `BITS_AXI); + $display("TUSER_BITS = %d", `TUSER_BITS); + $display("TUSER_FILL = %d", `TUSER_FILL); + $display("MASK_OUT = %x", `MASK_OUT); + + $monitor( + "cin 0b%b | reset_n 0b%b | axs_tready 0b%b | axs_tvalid 0b%b | axs_tdata 0x%h | axs_tlast 0x%h | axs_tuser 0x%h | aso_ready 0b%b | aso_valid 0b%b | aso_data 0x%h | aso_sop 0b%b | aso_endofpacket 0b%b | aso_empty 0b%b", + cin, reset_n, axs_tready, axs_tvalid, axs_tdata, axs_tlast, axs_tuser, aso_ready, + aso_valid, aso_data, aso_startofpacket, aso_endofpacket, aso_empty); + end + + logic [`BITS_PER_PIXEL_AXI-1:0] pixel1_axs; + logic [`BITS_PER_PIXEL_AXI-1:0] pixel2_axs; + + initial begin + @(negedge cin); + reset_n = 1'b1; + @(negedge cin); + axs_tvalid <= 1; + assign pixel1_axs = {2'b11, 10'h13, 10'h12, 10'h11}; + assign pixel2_axs = {2'b11, 10'h23, 10'h22, 10'h21}; + axs_tdata <= {pixel2_axs, pixel1_axs}; + axs_tlast <= 0; + axs_tuser <= 0; + + aso_ready <= 1; + @(negedge cin); + $stop; + end + +endmodule