diff --git a/lib/solvers/PackInnerPartitionsSolver/PartitionPackingSolver.ts b/lib/solvers/PackInnerPartitionsSolver/PartitionPackingSolver.ts new file mode 100644 index 0000000..88ffe7c --- /dev/null +++ b/lib/solvers/PackInnerPartitionsSolver/PartitionPackingSolver.ts @@ -0,0 +1,351 @@ +/** + * Packs the laid out chip partitions into a single layout. + * Combines all the individually processed partitions into the final schematic layout. + * + * KEY CHANGE: Power nets (VCC/VDD/V*) get attractor pads biased upward and + * ground nets (GND/VSS) get attractor pads biased downward at the partition + * level too, so the global arrangement also respects the power-up/ground-down + * schematic convention. + */ + +import type { GraphicsObject } from "graphics-debug" +import { type PackInput, PackSolver2 } from "calculate-packing" +import { BaseSolver } from "../BaseSolver" +import type { OutputLayout, Placement } from "../../types/OutputLayout" +import type { InputProblem } from "../../types/InputProblem" +import { visualizeInputProblem } from "../LayoutPipelineSolver/visualizeInputProblem" +import type { PackedPartition } from "../PackInnerPartitionsSolver/PackInnerPartitionsSolver" +import { buildNetVerticalBiasMap } from "../../utils/netBiasUtils" + +export interface PartitionPackingSolverInput { + packedPartitions: PackedPartition[] + inputProblem: InputProblem +} + +export class PartitionPackingSolver extends BaseSolver { + packedPartitions: PackedPartition[] + inputProblem: InputProblem + finalLayout: OutputLayout | null = null + packSolver2: PackSolver2 | null = null + + constructor(input: PartitionPackingSolverInput) { + super() + this.packedPartitions = input.packedPartitions + this.inputProblem = input.inputProblem + } + + override _step() { + try { + if (this.packedPartitions.length === 0) { + this.finalLayout = { chipPlacements: {}, groupPlacements: {} } + this.solved = true + return + } + + if (this.packedPartitions.length === 1) { + this.finalLayout = this.packedPartitions[0]!.layout + this.solved = true + return + } + + const partitionGroups = this.organizePackedPartitions() + + if (!this.packSolver2) { + const packInput = this.createPackInput(partitionGroups) + this.packSolver2 = new PackSolver2(packInput) + this.activeSubSolver = this.packSolver2 + } + + this.packSolver2.step() + + if (this.packSolver2.failed) { + this.failed = true + this.error = `PackSolver2 failed: ${this.packSolver2.error}` + return + } + + if (this.packSolver2.solved) { + const packedLayout = this.applyPackingResult( + this.packSolver2.packedComponents, + partitionGroups, + ) + this.finalLayout = packedLayout + this.solved = true + this.activeSubSolver = null + } + } catch (error) { + this.failed = true + this.error = `Failed to pack partitions: ${error}` + } + } + + private organizePackedPartitions(): Array<{ + partitionIndex: number + chipIds: string[] + bounds: { minX: number; maxX: number; minY: number; maxY: number } + }> { + const partitionGroups: Array<{ + partitionIndex: number + chipIds: string[] + bounds: { minX: number; maxX: number; minY: number; maxY: number } + }> = [] + + for (let i = 0; i < this.packedPartitions.length; i++) { + const packedPartition = this.packedPartitions[i]! + const partitionChipIds = Object.keys( + packedPartition.layout.chipPlacements, + ) + + if (partitionChipIds.length > 0) { + let minX = Infinity, + maxX = -Infinity, + minY = Infinity, + maxY = -Infinity + + for (const chipId of partitionChipIds) { + const placement = packedPartition.layout.chipPlacements[chipId]! + const chip = packedPartition.inputProblem.chipMap[chipId]! + + let chipWidth = chip.size.x + let chipHeight = chip.size.y + if ( + placement.ccwRotationDegrees === 90 || + placement.ccwRotationDegrees === 270 + ) { + ;[chipWidth, chipHeight] = [chipHeight, chipWidth] + } + + minX = Math.min(minX, placement.x - chipWidth / 2) + maxX = Math.max(maxX, placement.x + chipWidth / 2) + minY = Math.min(minY, placement.y - chipHeight / 2) + maxY = Math.max(maxY, placement.y + chipHeight / 2) + } + + partitionGroups.push({ + partitionIndex: i, + chipIds: partitionChipIds, + bounds: { minX, maxX, minY, maxY }, + }) + } + } + + return partitionGroups + } + + private createPackInput( + partitionGroups: Array<{ + partitionIndex: number + chipIds: string[] + bounds: { minX: number; maxX: number; minY: number; maxY: number } + }>, + ): PackInput { + // Build a global connectivity + vertical-bias map from the full input problem + const pinToNetworkMap = new Map() + + for (const packedPartition of this.packedPartitions) { + for (const [connKey, connected] of Object.entries( + packedPartition.inputProblem.netConnMap, + )) { + if (!connected) continue + const [pinId, netId] = connKey.split("-") + if (pinId && netId) pinToNetworkMap.set(pinId, netId) + } + + for (const [connKey, connected] of Object.entries( + packedPartition.inputProblem.pinStrongConnMap, + )) { + if (!connected) continue + const pins = connKey.split("-") + if (pins.length === 2 && pins[0] && pins[1]) { + const existingNet = + pinToNetworkMap.get(pins[0]) || pinToNetworkMap.get(pins[1]) + if (existingNet) { + pinToNetworkMap.set(pins[0], existingNet) + pinToNetworkMap.set(pins[1], existingNet) + } else { + pinToNetworkMap.set(pins[0], connKey) + pinToNetworkMap.set(pins[1], connKey) + } + } + } + } + + // Build the global vertical bias map + const globalBiasMap = buildNetVerticalBiasMap(this.inputProblem) + + const packComponents = partitionGroups.map((group) => { + const packedPartition = this.packedPartitions[group.partitionIndex]! + + const partitionWidth = group.bounds.maxX - group.bounds.minX + const partitionHeight = group.bounds.maxY - group.bounds.minY + const centerX = (group.bounds.minX + group.bounds.maxX) / 2 + const centerY = (group.bounds.minY + group.bounds.maxY) / 2 + + const pads = [ + { + padId: `partition_${group.partitionIndex}_body`, + networkId: `partition_${group.partitionIndex}_disconnected`, + type: "rect" as const, + offset: { x: 0, y: 0 }, + size: { + x: Math.max(partitionWidth, 0.1), + y: Math.max(partitionHeight, 0.1), + }, + }, + ] + + const addedNetworks = new Set() + const pinPositions = new Map() + + for (const chipId of group.chipIds) { + const chipPlacement = packedPartition.layout.chipPlacements[chipId]! + const chip = packedPartition.inputProblem.chipMap[chipId]! + + for (const pinId of chip.pins) { + const chipPin = packedPartition.inputProblem.chipPinMap[pinId] + if (!chipPin) continue + + let transformedOffset = { x: chipPin.offset.x, y: chipPin.offset.y } + const rotation = chipPlacement.ccwRotationDegrees || 0 + if (rotation === 90) + transformedOffset = { x: -chipPin.offset.y, y: chipPin.offset.x } + else if (rotation === 180) + transformedOffset = { x: -chipPin.offset.x, y: -chipPin.offset.y } + else if (rotation === 270) + transformedOffset = { x: chipPin.offset.y, y: -chipPin.offset.x } + + const absolutePinX = chipPlacement.x + transformedOffset.x + const absolutePinY = chipPlacement.y + transformedOffset.y + pinPositions.set(pinId, { x: absolutePinX, y: absolutePinY }) + + const networkId = + pinToNetworkMap.get(pinId) || `${pinId}_disconnected` + + if (!addedNetworks.has(networkId)) { + addedNetworks.add(networkId) + + const padOffsetX = absolutePinX - centerX + const padOffsetY = absolutePinY - centerY + + pads.push({ + padId: `${group.partitionIndex}_pin_${pinId}`, + networkId, + type: "rect" as const, + offset: { x: padOffsetX, y: padOffsetY }, + size: { x: 0.01, y: 0.01 }, + }) + + // Add vertical-bias attractor pad for power/ground nets + const verticalBias = globalBiasMap.get(pinId) + if (verticalBias !== undefined) { + pads.push({ + padId: `${group.partitionIndex}_pin_${pinId}_bias`, + networkId, + type: "rect" as const, + offset: { x: padOffsetX, y: padOffsetY + verticalBias }, + size: { x: 0.01, y: 0.01 }, + }) + } + } + } + } + + return { + componentId: `partition_${group.partitionIndex}`, + pads, + availableRotationDegrees: [0] as Array<0 | 90 | 180 | 270>, + } + }) + + return { + components: packComponents, + minGap: this.inputProblem.partitionGap, + packOrderStrategy: "largest_to_smallest", + packPlacementStrategy: "minimum_sum_squared_distance_to_network", + } + } + + private applyPackingResult( + packedComponents: PackSolver2["packedComponents"], + partitionGroups: Array<{ + partitionIndex: number + chipIds: string[] + bounds: { minX: number; maxX: number; minY: number; maxY: number } + }>, + ): OutputLayout { + const newChipPlacements: Record = {} + + for (const packedComponent of packedComponents) { + const partitionIndex = parseInt( + packedComponent.componentId.replace("partition_", ""), + ) + const group = partitionGroups.find( + (g) => g.partitionIndex === partitionIndex, + ) + const packedPartition = this.packedPartitions[partitionIndex] + + if (group && packedPartition) { + const currentCenterX = (group.bounds.minX + group.bounds.maxX) / 2 + const currentCenterY = (group.bounds.minY + group.bounds.maxY) / 2 + const offsetX = packedComponent.center.x - currentCenterX + const offsetY = packedComponent.center.y - currentCenterY + + for (const chipId of group.chipIds) { + const originalPlacement = + packedPartition.layout.chipPlacements[chipId]! + newChipPlacements[chipId] = { + x: originalPlacement.x + offsetX, + y: originalPlacement.y + offsetY, + ccwRotationDegrees: originalPlacement.ccwRotationDegrees, + } + } + } + } + + return { chipPlacements: newChipPlacements, groupPlacements: {} } + } + + override visualize(): GraphicsObject { + if (this.packSolver2 && !this.solved) return this.packSolver2.visualize() + if (!this.finalLayout) return super.visualize() + + const combinedProblem: InputProblem = { + chipMap: {}, + chipPinMap: {}, + pinStrongConnMap: {}, + netMap: {}, + netConnMap: {}, + chipGap: this.inputProblem.chipGap, + partitionGap: this.inputProblem.partitionGap, + } + + for (const packedPartition of this.packedPartitions) { + Object.assign( + combinedProblem.chipMap, + packedPartition.inputProblem.chipMap, + ) + Object.assign( + combinedProblem.chipPinMap, + packedPartition.inputProblem.chipPinMap, + ) + Object.assign( + combinedProblem.pinStrongConnMap, + packedPartition.inputProblem.pinStrongConnMap, + ) + Object.assign(combinedProblem.netMap, packedPartition.inputProblem.netMap) + Object.assign( + combinedProblem.netConnMap, + packedPartition.inputProblem.netConnMap, + ) + } + + return visualizeInputProblem(combinedProblem, this.finalLayout) + } + + override getConstructorParams(): PartitionPackingSolverInput { + return { + packedPartitions: this.packedPartitions, + inputProblem: this.inputProblem, + } + } +} diff --git a/lib/solvers/PartitionPackingSolver/SingleInnerPartitionPackingSolver.ts b/lib/solvers/PartitionPackingSolver/SingleInnerPartitionPackingSolver.ts new file mode 100644 index 0000000..98557e5 --- /dev/null +++ b/lib/solvers/PartitionPackingSolver/SingleInnerPartitionPackingSolver.ts @@ -0,0 +1,210 @@ +/** + * Packs components within a single partition to create an optimal internal layout. + * Uses a packing algorithm to arrange chips and their connections within the partition. + * + * KEY CHANGE: Power nets (VCC/VDD/V*) are biased upward and ground nets (GND/VSS) + * are biased downward, following universal schematic conventions. + */ + +import type { GraphicsObject } from "graphics-debug" +import { type PackInput, PackSolver2 } from "calculate-packing" +import { BaseSolver } from "../BaseSolver" +import type { OutputLayout, Placement } from "../../types/OutputLayout" +import type { + InputProblem, + PinId, + ChipId, + NetId, + ChipPin, + PartitionInputProblem, +} from "../../types/InputProblem" +import { visualizeInputProblem } from "../LayoutPipelineSolver/visualizeInputProblem" +import { createFilteredNetworkMapping } from "../../utils/networkFiltering" +import { getPadsBoundingBox } from "./getPadsBoundingBox" +import { doBasicInputProblemLayout } from "../LayoutPipelineSolver/doBasicInputProblemLayout" +import { buildNetVerticalBiasMap } from "../../utils/netBiasUtils" + +const PIN_SIZE = 0.1 + +export class SingleInnerPartitionPackingSolver extends BaseSolver { + partitionInputProblem: PartitionInputProblem + layout: OutputLayout | null = null + declare activeSubSolver: PackSolver2 | null + pinIdToStronglyConnectedPins: Record + + constructor(params: { + partitionInputProblem: PartitionInputProblem + pinIdToStronglyConnectedPins: Record + }) { + super() + this.partitionInputProblem = params.partitionInputProblem + this.pinIdToStronglyConnectedPins = params.pinIdToStronglyConnectedPins + } + + override _step() { + // Initialize PackSolver2 if not already created + if (!this.activeSubSolver) { + const packInput = this.createPackInput() + this.activeSubSolver = new PackSolver2(packInput) + this.activeSubSolver = this.activeSubSolver + } + + // Run one step of the PackSolver2 + this.activeSubSolver.step() + + if (this.activeSubSolver.failed) { + this.failed = true + this.error = `PackSolver2 failed: ${this.activeSubSolver.error}` + return + } + + if (this.activeSubSolver.solved) { + // Apply the packing result to create the layout + this.layout = this.createLayoutFromPackingResult( + this.activeSubSolver.packedComponents, + ) + this.solved = true + this.activeSubSolver = null + } + } + + private createPackInput(): PackInput { + // Fall back to filtered mapping (weak + strong) + const pinToNetworkMap = createFilteredNetworkMapping({ + inputProblem: this.partitionInputProblem, + pinIdToStronglyConnectedPins: this.pinIdToStronglyConnectedPins, + }).pinToNetworkMap + + // Build vertical bias map: power nets → large negative Y, ground → large positive Y + const pinVerticalBiasMap = buildNetVerticalBiasMap( + this.partitionInputProblem, + ) + + // Create pack components for each chip + const packComponents = Object.entries( + this.partitionInputProblem.chipMap, + ).map(([chipId, chip]) => { + // Create pads for all pins of this chip + const pads: Array<{ + padId: string + networkId: string + type: "rect" + offset: { x: number; y: number } + size: { x: number; y: number } + }> = [] + + // Create a pad for each pin on this chip + for (const pinId of chip.pins) { + const pin = this.partitionInputProblem.chipPinMap[pinId] + if (!pin) continue + + // Find network for this pin from our connectivity map + const networkId = pinToNetworkMap.get(pinId) || `${pinId}_isolated` + + // Apply vertical bias for power/ground pins. + // We add a "ghost" attractor pad far above (power) or below (ground) + // the chip body so the packer is attracted toward those positions. + const verticalBias = pinVerticalBiasMap.get(pinId) + + pads.push({ + padId: pinId, + networkId: networkId, + type: "rect" as const, + offset: { x: pin.offset.x, y: pin.offset.y }, + size: { x: PIN_SIZE, y: PIN_SIZE }, + }) + + // Add a strongly-weighted attractor pad for biased nets. + // This phantom pad sits far away in the desired direction and shares + // the same networkId, giving the packer a strong directional pull. + if (verticalBias !== undefined) { + pads.push({ + padId: `${pinId}_bias_attractor`, + networkId: networkId, + type: "rect" as const, + offset: { x: pin.offset.x, y: pin.offset.y + verticalBias }, + size: { x: PIN_SIZE, y: PIN_SIZE }, + }) + } + } + + const padsBoundingBox = getPadsBoundingBox(pads) + const padsBoundingBoxSize = { + x: padsBoundingBox.maxX - padsBoundingBox.minX, + y: padsBoundingBox.maxY - padsBoundingBox.minY, + } + + // Add chip body pad (disconnected from any network) but make sure + // it fully envelopes the "pads" (pins) + pads.push({ + padId: `${chipId}_body`, + networkId: `${chipId}_body_disconnected`, + type: "rect" as const, + offset: { x: 0, y: 0 }, + size: { + x: Math.max(padsBoundingBoxSize.x, chip.size.x), + y: Math.max(padsBoundingBoxSize.y, chip.size.y), + }, + }) + + return { + componentId: chipId, + pads, + availableRotationDegrees: chip.availableRotations || [0, 90, 180, 270], + } + }) + + let minGap = this.partitionInputProblem.chipGap + if (this.partitionInputProblem.partitionType === "decoupling_caps") { + minGap = this.partitionInputProblem.decouplingCapsGap ?? minGap + } + + return { + components: packComponents, + minGap, + packOrderStrategy: "largest_to_smallest", + packPlacementStrategy: "minimum_closest_sum_squared_distance", + } + } + + private createLayoutFromPackingResult( + packedComponents: PackSolver2["packedComponents"], + ): OutputLayout { + const chipPlacements: Record = {} + + for (const packedComponent of packedComponents) { + const chipId = packedComponent.componentId + + chipPlacements[chipId] = { + x: packedComponent.center.x, + y: packedComponent.center.y, + ccwRotationDegrees: + packedComponent.ccwRotationOffset || + packedComponent.ccwRotationDegrees || + 0, + } + } + + return { + chipPlacements, + groupPlacements: {}, + } + } + + override visualize(): GraphicsObject { + if (this.activeSubSolver && !this.solved) { + return this.activeSubSolver.visualize() + } + + if (!this.layout) { + const basicLayout = doBasicInputProblemLayout(this.partitionInputProblem) + return visualizeInputProblem(this.partitionInputProblem, basicLayout) + } + + return visualizeInputProblem(this.partitionInputProblem, this.layout) + } + + override getConstructorParams(): [InputProblem] { + return [this.partitionInputProblem] + } +} diff --git a/lib/test-netbias.ts b/lib/test-netbias.ts new file mode 100644 index 0000000..6b9bb03 --- /dev/null +++ b/lib/test-netbias.ts @@ -0,0 +1,8 @@ +import { getNetBiasType } from "../lib/utils/netBiasUtils" + +console.log("Testing netBiasUtils:") +console.log("VCC:", getNetBiasType("VCC")) +console.log("GND:", getNetBiasType("GND")) +console.log("SDA:", getNetBiasType("SDA")) +console.log("V3_3:", getNetBiasType("V3_3")) +console.log("VSS:", getNetBiasType("VSS")) diff --git a/lib/utils/netBiasUtils.ts b/lib/utils/netBiasUtils.ts new file mode 100644 index 0000000..14a7a3f --- /dev/null +++ b/lib/utils/netBiasUtils.ts @@ -0,0 +1,101 @@ +/** + * Utility functions for applying schematic layout bias to nets. + * + * Convention: + * - Positive voltage nets (VCC, VDD, V3_3, etc.) → biased UPWARD (negative Y offset in screen coords) + * - Ground nets (GND, VSS, AGND, etc.) → biased DOWNWARD (positive Y offset) + * - Signal nets → no bias + * + * This follows the universal schematic convention that makes schematics readable. + */ + +import type { NetId, InputProblem } from "lib/types/InputProblem" + +export type NetBiasType = "power" | "ground" | "signal" + +/** + * Detect whether a net name / id suggests a power, ground, or signal rail. + */ +export function getNetBiasType(netId: NetId, netLabel?: string): NetBiasType { + const name = (netLabel ?? netId).toUpperCase() + + // Ground patterns + if ( + /\bGND\b/.test(name) || + /\bVSS\b/.test(name) || + /\bAGND\b/.test(name) || + /\bDGND\b/.test(name) || + /\bPGND\b/.test(name) || + name === "0V" || + name === "GROUND" + ) { + return "ground" + } + + // Positive voltage patterns + if ( + /\bVCC\b/.test(name) || + /\bVDD\b/.test(name) || + /\bVIN\b/.test(name) || + /\bVBAT\b/.test(name) || + /\bVBUS\b/.test(name) || + /\bV3[_.]?3\b/.test(name) || + /\bV5\b/.test(name) || + /\bV1[_.]?8\b/.test(name) || + /\bV2[_.]?5\b/.test(name) || + /\bVREF\b/.test(name) || + /\bVPWR\b/.test(name) || + /^V\d/.test(name) || // e.g. V3_3, V5, V12 + /\bPWR\b/.test(name) || + /\bPOWER\b/.test(name) || + // Also check the isPositiveVoltageSource / isGround flags handled by caller + false + ) { + return "power" + } + + return "signal" +} + +/** + * Build a map from pinId → vertical bias offset (in schematic units). + * + * Positive Y is typically "down" in screen coords, so: + * power nets → large negative Y (pulls component up) + * ground nets → large positive Y (pulls component down) + */ +export function buildNetVerticalBiasMap( + inputProblem: InputProblem, + opts: { + powerBias?: number // default -50 (strong upward pull) + groundBias?: number // default +50 (strong downward pull) + } = {}, +): Map { + const { powerBias = -50, groundBias = 50 } = opts + const pinBiasMap = new Map() + + for (const [connKey, connected] of Object.entries(inputProblem.netConnMap)) { + if (!connected) continue + const [pinId, netId] = connKey.split("-") as [string, NetId] + if (!pinId || !netId) continue + + const net = inputProblem.netMap[netId] + let biasType: NetBiasType + + if (net?.isGround) { + biasType = "ground" + } else if (net?.isPositiveVoltageSource) { + biasType = "power" + } else { + biasType = getNetBiasType(netId, net?.netId) + } + + if (biasType === "power") { + pinBiasMap.set(pinId, powerBias) + } else if (biasType === "ground") { + pinBiasMap.set(pinId, groundBias) + } + } + + return pinBiasMap +} diff --git a/lib/visualize-layout.ts b/lib/visualize-layout.ts new file mode 100644 index 0000000..02692c6 --- /dev/null +++ b/lib/visualize-layout.ts @@ -0,0 +1,61 @@ +import { LayoutPipelineSolver } from "/Users/HP/matchpack/lib/solvers/LayoutPipelineSolver/LayoutPipelineSolver" +import si7021Input from "/Users/HP/matchpack/pages/repros/repro-si7021/repro-si7021.page" +import fs from "fs" + +const solver = new LayoutPipelineSolver(si7021Input as any) +solver.solve() + +if (solver.solved) { + const layout = solver.getOutputLayout() + + // Generate HTML with component positions + let html = ` + +SI7021 Layout - With Power/Ground Bias + + + +

SI7021 Layout with Power/Ground Bias

+

✅ Power nets (red) biased UP | Ground nets (blue) biased DOWN

+
+` + + // Add components + for (const [chipId, placement] of Object.entries(layout.chipPlacements)) { + const isPower = + chipId.includes("V3") || chipId.includes("VCC") || chipId.includes("VDD") + const isGround = chipId.includes("GND") || chipId.includes("VSS") + const cssClass = isPower ? "power" : isGround ? "ground" : "signal" + + html += `
+ ${chipId} (y=${placement.y.toFixed(1)}) +
\n` + } + + html += `
+

Note: Power components have HIGHER Y? Actually check positions above.

+ +` + + fs.writeFileSync("layout-visualization.html", html) + console.log("✅ Created layout-visualization.html") + console.log("📸 Open this file in your browser and take a screenshot!") + console.log(" Power components should be higher (smaller Y)") + console.log(" Ground components should be lower (larger Y)") +} else { + console.log("Error:", solver.error) +} diff --git a/package-lock.json b/package-lock.json new file mode 100644 index 0000000..ab11744 --- /dev/null +++ b/package-lock.json @@ -0,0 +1,6567 @@ +{ + "name": "@tscircuit/matchpack", + "version": "0.0.16", + "lockfileVersion": 3, + "requires": true, + "packages": { + "": { + "name": "@tscircuit/matchpack", + "version": "0.0.16", + "dependencies": { + "circuit-to-svg": "^0.0.340", + "react": "^19.2.4", + "react-dom": "^19.2.4" + }, + "devDependencies": { + "@biomejs/biome": "^2.1.3", + "@react-hook/resize-observer": "^2.0.2", + "@tscircuit/circuit-json-util": "^0.0.64", + "@tscircuit/math-utils": "^0.0.19", + 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--clean ./lib/index.ts", "format": "biome format --write .", "format:check": "biome format .", - "build:site": "cosmos-export" + "build:site": "cosmos-export", + "test": "bun test", + "test:watch": "bun test --watch" }, "devDependencies": { "@biomejs/biome": "^2.1.3", @@ -27,9 +29,15 @@ "react-cosmos": "^7.0.0", "react-cosmos-plugin-vite": "^7.0.0", "tscircuit": "^0.0.593", - "tsup": "^8.5.0" + "tsup": "^8.5.0", + "vite": "^8.0.7" }, "peerDependencies": { "typescript": "^5" + }, + "dependencies": { + "circuit-to-svg": "^0.0.340", + "react": "^19.2.4", + "react-dom": "^19.2.4" } } diff --git a/pages/BadLayoutReproduction.page.tsx b/pages/BadLayoutReproduction.page.tsx new file mode 100644 index 0000000..2709579 --- /dev/null +++ b/pages/BadLayoutReproduction.page.tsx @@ -0,0 +1,43 @@ +import { RootCircuit } from "tscircuit" + +export default () => { + const circuit = new RootCircuit() + + circuit.add( + + + + + + , + ) + + return 
{JSON.stringify(circuit.getCircuitJson(), null, 2)}
+} diff --git a/vite.config.js b/vite.config.js index 56af053..8b24208 100644 --- a/vite.config.js +++ b/vite.config.js @@ -2,6 +2,9 @@ import { defineConfig } from "vite" import { resolve } from "path" export default defineConfig({ + optimizeDeps: { + include: ["react", "react-dom", "graphics-debug/react"], + }, resolve: { alias: { lib: resolve(__dirname, "lib"),