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Figure out the ABI for the ibm-aix target (vec-default vs vec-extabi) #153876
Description
Disclaimer: I know little about PowerPC and even less about AIX. So maybe I'm wrong about all this. Someone please confirm whether any of this makes sense. :)
AIX on Power64 has two possible ABIs: vec-default and vec-extabi. In LLVM, the EnableAIXExtendedAltivecABI field controls which ABI is actually used. In Rust, we also have the abi field on each target which controls cfg(target_abi), but usually (and in particular in this case) doesn't itself have any effect on the ABI -- it merely informs the programmer which ABI the target spec claims to implement, but as target spec author one still has to manually arrange for that ABI to actually be used (in a usually architecture-specific manner, because ABIs are a mess so nothing is consistent).
The powerpc64-ibm-aix target got added in #102293, with cfg(target_abi) indicating "vec-extabi", but without setting EnableAIXExtendedAltivecABI, leaving it at its default value of false. In other words, the target claims via cfg(target_abi) to use vec-extabi, but actually it used vec-default. That seems inconsistent and we should fix it.
In #153784, the proposal was to fix this by actually setting EnableAIXExtendedAltivecABI in LLVM. However, @daltenty raised the concern that this might not actually be what the target maintainers want. So in #153830 I proposed to instead fix the problem by changing cfg(target_abi) to "vec-default", matching the (implied default) value of EnableAIXExtendedAltivecABI. But that clashes with logic in our inline assembly handling which rejects using the registers v20-v31 (vs52-vs63) when cfg(target_abi) is "vec-default" (#131341, #146949).
I don't know what the correct fix here is, so I figured I'd just open an issue, dump everything I know, ping all the right people, and let you all figure it out. :) In particular, it is confusing to me that the inline assembly logic looks at the ABI -- whether the registers are available and whether they get used by the ABI are usually orthogonal questions, and it would seem to me that inline asm should care about the former, not the latter. But I also don't know how availability of these registers is modeled on AIX/PowerPC; on other architectures, this is typically done via target features.
Cc @Gelbpunkt @daltenty @gilamn5tr @amy-kwan @ecnelises @pmur @taiki-e @Amanieu @workingjubilee