From 5fbf196198fa327685f813a73462d1cf53c237f9 Mon Sep 17 00:00:00 2001
From: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Date: Wed, 25 Mar 2026 12:07:43 +0530
Subject: [PATCH] arm64: dts: qcom: Add RPM, MPM and apcs_glb devices for
 shikra

Add RPM and RPM msg ram devices for APSS-RPM communication.
Add MPM interrupt controller and apcs_glb devices.
Also add MPM as wakeup parent to TLMM device.

Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 59 ++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index d5076652660a..8e946cf5b840 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -91,6 +91,41 @@
 		};
 	};
 
+	rpm: remoteproc {
+		compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc";
+
+		glink-edge {
+			compatible = "qcom,glink-rpm";
+			interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+			qcom,rpm-msg-ram = <&rpm_msg_ram>;
+			mboxes = <&apcs_glb 0>;
+
+			rpm_requests: rpm-requests {
+				compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm";
+				qcom,glink-channels = "rpm_requests";
+			};
+		};
+
+		mpm: interrupt-controller {
+			compatible = "qcom,mpm";
+			qcom,rpm-msg-ram = <&apss_mpm>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&apcs_glb 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#power-domain-cells = <0>;
+			interrupt-parent = <&intc>;
+			qcom,mpm-pin-count = <95>;
+			qcom,mpm-pin-map = <2 275>,  /* TSENS0 uplow */
+					   <12 422>, /* DWC3 ss_phy_irq */
+					   <58 272>, /* QUSB2_PHY dmse_hv_vddmx */
+					   <59 273>, /* QUSB2_PHY dpse_hv_vddmx */
+					   <86 183>, /* MPM wake, SPMI */
+					   <90 157>, /* QUSB2_PHY DM */
+					   <91 158>; /* QUSB2_PHY DP */
+		};
+	};
+
 	memory@a0000000 {
 		device_type = "memory";
 		/* We expect the bootloader to fill in the size */
@@ -128,6 +163,7 @@
 			#interrupt-cells = <2>;
 
 			gpio-ranges = <&tlmm 0 0 185>;
+			wakeup-parent = <&mpm>;
 
 			qup_uart0_default: qup-uart0-default-state {
 				pins = "gpio0", "gpio1";
@@ -137,6 +173,23 @@
 			};
 		};
 
+		rpm_msg_ram: sram@45f0000 {
+			compatible = "qcom,rpm-msg-ram", "mmio-sram";
+			reg = <0x0 0x045f0000 0x0 0x7000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x0 0x045f0000 0x7000>;
+
+			apss_mpm: sram@1b8 {
+				reg = <0x1b8 0x48>;
+			};
+		};
+
+		sram@4690000 {
+			compatible = "qcom,rpm-stats";
+			reg = <0x0 0x04690000 0x0 0x14000>;
+		};
+
 		sram@c11e000 {
 			compatible = "qcom,shikra-imem", "syscon", "simple-mfd";
 			reg = <0x0 0x0c11e000 0x0 0x1000>;
@@ -169,6 +222,12 @@
 			ranges;
 		};
 
+		apcs_glb: mailbox@f400000 {
+			compatible = "qcom,shikra-apcs-hmss-global";
+			reg = <0x0 0x0f400000 0x0 0x1000>;
+			#mbox-cells = <1>;
+		};
+
 		timer@f420000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0 0x0f420000  0x0 0x1000>;