diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 1078de779c16e..45c39be16e96d 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -29,10 +29,14 @@ properties: maxItems: 1 clocks: + minItems: 1 maxItems: 2 clock-names: - maxItems: 2 + minItems: 1 + items: + - const: core + - const: iface power-domains: maxItems: 1 @@ -41,11 +45,28 @@ required: - compatible - reg - clocks - - clock-names - - power-domains additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-inline-crypto-engine + - qcom,milos-inline-crypto-engine + + then: + required: + - power-domains + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + examples: - | #include @@ -56,8 +77,8 @@ examples: reg = <0x01d88000 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; ... diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 9ef57ad0ca71d..52af56e091689 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -868,7 +868,11 @@ "qcom,inline-crypto-engine"; reg = <0x0 0x01d88000 0x0 0x18000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; tcsr_mutex: hwlock@1f40000 { diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 6bdc932021229..e48af314a9487 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2590,8 +2590,8 @@ reg = <0 0x01d88000 0 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 4473aa8bd5f43..6b8c81ceddee5 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2760,8 +2760,8 @@ reg = <0x0 0x01d88000 0x0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d4e05f9acdb5d..0339ba653a09e 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2727,8 +2727,8 @@ reg = <0x0 0x01d88000 0x0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 74eb895cf4da7..d6e01aca4c5a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1607,8 +1607,8 @@ reg = <0 0x01d90000 0 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 3d243e757fa1a..d763f7205641b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5376,8 +5376,8 @@ reg = <0 0x01d88000 0 0x8000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index b6c8c76429ba9..473fb47480361 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2451,8 +2451,8 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index c32a817efdb47..d211bd94fb413 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4083,8 +4083,8 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc UFS_PHY_GDSC>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index e870bdf2528c2..8c33bc3620ef0 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2085,8 +2085,8 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>; - clock-names = "ice_core_clk", - "iface_clk"; + clock-names = "core", + "iface"; power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 4b50d05ca02a3..bf4ab2d9e5c03 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,8 +16,6 @@ #include #include #include -#include -#include #include @@ -313,18 +311,15 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev = ice->dev; int err; - pm_runtime_get_sync(dev); err = clk_prepare_enable(ice->core_clk); if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + dev_err(dev, "Failed to enable core clock: %d\n", err); return err; } err = clk_prepare_enable(ice->iface_clk); if (err) { - dev_err(dev, "failed to enable iface clock (%d)\n", - err); + dev_err(dev, "Failed to enable iface clock: %d\n", err); return err; } qcom_ice_hwkm_init(ice); @@ -336,7 +331,6 @@ int qcom_ice_suspend(struct qcom_ice *ice) { clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); - pm_runtime_put_sync(ice->dev); ice->hwkm_init_complete = false; return 0; @@ -592,12 +586,14 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); if (!engine->core_clk) engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_optional_enabled(dev, "core"); if (!engine->core_clk) engine->core_clk = devm_clk_get_enabled(dev, NULL); if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); - engine->iface_clk = devm_clk_get_enabled(dev, "iface_clk"); + engine->iface_clk = devm_clk_get_optional_enabled(dev, "iface"); if (IS_ERR(engine->iface_clk)) return ERR_CAST(engine->iface_clk); @@ -742,9 +738,6 @@ static int qcom_ice_probe(struct platform_device *pdev) return PTR_ERR(base); } - devm_pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - engine = qcom_ice_create(&pdev->dev, base); if (IS_ERR(engine)) return PTR_ERR(engine);