Flash.dev

// File: Flash.dev
// '//' is a comment until the end of the line, not allowed in cycles yet!

// try '(gdb) set mpcbdm_verbose 0x40' for flash configuration parsing output
// then '(gdb) mp flash conf 0x40000000 2 AM29LV160DB' for 2 16 bit devices

// this .device section defines a available device name
.device AM29LV160DB
{
	.size 2M				//size in bytes for one device, K and M suffixes supported
	.width 16				//width in bits for one device
	.sector AM29LV160DB		//name of following .sector section to be used with this device
	.idoffset 12			//shift first entry of .sector n bits to left for ID ADR
	.algorithm AMD4			//name of following .algorithm section to be used with this device
}

.device AM29LV800BT
{
	.size 1M			//size in bytes for one device, K and M suffixes supported
	.width 16			//width in bits for one device
	.sector AM29LV800BT		//name of following .sector section to be used with this device
	.idoffset 12			//shift first entry of .sector n bits to left for ID ADR
	.algorithm AMD4			//name of following .algorithm section to be used with this device
}

.device MX29LV800TMC
{
	.size 1M			//size in bytes for one device, K and M suffixes supported
	.width 16			//width in bits for one device
	.sector AM29LV800BT		//name of following .sector section to be used with this device
	.idoffset 12			//shift first entry of .sector n bits to left for ID ADR
	.algorithm TMC			//name of following .algorithm section to be used with this device
}

// The .sector section is referenced from the above .device section
// and describes the internal device sector structure
//  ID	, start	, stop
.sector AM29LV160DB
{
	0x00,0x00000,0x01fff,
	0x02,0x02000,0x02fff,
	0x03,0x03000,0x03fff,
	0x04,0x04000,0x07fff,
	0x08,0x08000,0x0ffff,
	0x10,0x10000,0x17fff,
	0x18,0x18000,0x1ffff,
	0x20,0x20000,0x27fff,
	0x28,0x28000,0x2ffff,
	0x30,0x30000,0x37fff,
	0x38,0x38000,0x3ffff,
	0x40,0x40000,0x47fff,
	0x48,0x48000,0x4ffff,
	0x50,0x50000,0x57fff,
	0x58,0x58000,0x5ffff,
	0x60,0x60000,0x67fff,
	0x68,0x68000,0x6ffff,
	0x70,0x70000,0x77fff,
	0x78,0x78000,0x7ffff,
	0x80,0x80000,0x87fff,
	0x88,0x88000,0x8ffff,
	0x90,0x90000,0x97fff,
	0x98,0x98000,0x9ffff,
	0xa0,0xa0000,0xa7fff,
	0xa8,0xa8000,0xaffff,
	0xb0,0xb0000,0xb7fff,
	0xb8,0xb8000,0xbffff,
	0xc0,0xc0000,0xc7fff,
	0xc8,0xc8000,0xcffff,
	0xd0,0xd0000,0xd7fff,
	0xd8,0xd8000,0xdffff,
	0xe0,0xe0000,0xe7fff,
	0xe8,0xe8000,0xeffff,
	0xf0,0xf0000,0xf7fff,
	0xf8,0xf8000,0xfffff
}

.sector AM29LV800BT
{
	0x00,0x00000,0x07fff,
	0x08,0x08000,0x0ffff,
	0x10,0x10000,0x17fff,
	0x18,0x18000,0x1ffff,
	0x20,0x20000,0x27fff,
	0x28,0x28000,0x2ffff,
	0x30,0x30000,0x37fff,
	0x38,0x38000,0x3ffff,
	0x40,0x40000,0x47fff,
	0x48,0x48000,0x4ffff,
	0x50,0x50000,0x57fff,
	0x58,0x58000,0x5ffff,
	0x60,0x60000,0x67fff,
	0x68,0x68000,0x6ffff,
	0x70,0x70000,0x77fff,
	0X74,0x78000,0x7bfff,
	0x75,0x7c000,0x7cfff,
	0x76,0x7d000,0x7dfff,
	0x7a,0x7e000,0x7ffff
}

// The .algorithm section is referenced from the above .device section
// and defines the programming method for the device.
// So far there are five sequences defined: .reset for getting the device back into
// read array mode, .ident for testing device presense, .write to program one word
// .erase for one sector erasing, .clear for chip wide erasing.
// .cfast defines register preloading for the fast target sided flashing routines
// .fast references the machine code to be used
// each sequence can be composed out of one or more cycles.
// There are five cycle types (operations) so far :
// Write (w) Read (r) Compare (r) Toggle (t) Poll (p) .
// Each cycle takes an ADR and a data word tupel: 'w0x0:0xf0'
// ADR can be immediate (e.g. 0x0) or actual ADR %A, both will be automaticaly adjusted
// for device offset and width
// Data can be immediate (e.g. 0x) or actual data word %D,
// both will be expanded to data bus width.
// Read generates a warning only if results differ, while Compare will exit with 
// failure status.
// Toggle reads from address, ANDs the result with the given mask and waits
// until the result stabilizes, as Poll waits for a zero result.
.algorithm AMD4
{
	.reset	w0x0:0xf0
	.ident	w0x555:0x00aa, w0x2aa:0x0055, w0x555:0x90,
			c0x000:0x0001, c0x001:0x2249, w0x000:0xf0
	.write	w0x555:0xaa, w0x2aa:0x55, w0x555:0xa0, w%A:%D, t%A:0x0040, r%A:%D 
	.erase	w0x555:0xaa, w0x2aa:0x55, w0x555:0x80,
			w0x555:0xaa, w0x2aa:0x55, w%I:0x30,	t%A:0x0040, r%A:0xffff
	.clear	w0x555:0xaa, w0x2aa:0x55, w0x555:0x80,
			w0x555:0xaa, w0x2aa:0x55, w0x555:0x10, t%A:0x0040, r%A:0xffff
//	.cfast	w0x555:0xaa, w0x2aa:0x55, w0x555:0xa0, w%A:%D
	.cfast	w0x555:0xaa, w0x2aa:0x55, w0x555:0xa0
// preload    r1    r2     r3    r4     r5    r6
	.fast	AMD4	// use .fast<bus_width> AMD4 section for fast flashing
}

.algorithm TMC
{
	.reset	w0x0:0xf0
	.ident	w0x555:0x00aa, w0x2aa:0x0055, w0x555:0x90,
			c0x000:0x00c2, c0x001:0x22da, w0x000:0xf0
	.write	w0x555:0xaa, w0x2aa:0x55, w0x555:0xa0, w%A:%D, t%A:0x0040, r%A:%D 
	.erase	w0x555:0xaa, w0x2aa:0x55, w0x555:0x80,
			w0x555:0xaa, w0x2aa:0x55, w%I:0x30,	t%A:0x0040, r%A:0xffff
	.clear	w0x555:0xaa, w0x2aa:0x55, w0x555:0x80,
			w0x555:0xaa, w0x2aa:0x55, w0x555:0x10, t%A:0x0040, r%A:0xffff
//	.cfast	w0x555:0xaa, w0x2aa:0x55, w0x555:0xa0, w%A:%D
	.cfast	w0x555:0xaa, w0x2aa:0x55, w0x555:0xa0
// preload    r1    r2     r3    r4     r5    r6
	.fast	AMD4	// use .fast<bus_width> AMD4 section for fast flashing
}

// the .fast sections contain target machine code to do a CTR based
// flash program loop. r28 points to the new data buffer -4 , r29 points
// to the write address -4, r1..rn get preloaded with .cfast values.
// SEI is used as return from target sub routine
// (some kind of distributed computing ;-)

// 32 bit flash ppc subroutine
.fast32 AMD4
{
// <flash32>:
	0x877c0004,	//   lwzu	 r27,4(r28)
	0x875d0004,	//   lwzu	 r26,4(r29)
	0x90410000,	//   stw r2,0(r1)
	0x90830000,	//   stw r4,0(r3)
	0x90c50000,	//   stw r6,0(r5)
	0x937d0000,	//   stw r27,0(r29)
//<toggle32>:
	0x7f59d378,	//   mr  r25,r26
	0x7c0006ac,	//   eieio
	0x835d0000,	//   lwz r26,0(r29)
	0x7c1bd040,	//   cmplw   r27,r26
	0x41820018,	//   beq <cont32>
	0x7f59ca79,	//   xor.	 r25,r26,r25
	0x4082ffe8,	//   bne <toggle32>
	0x835d0000,	//   lwz r26,0(r29)
	0x7c1bd040,	//   cmplw   r27,r26
	0x40820008,	//   bne <exit32>
//<cont32>:
	0x4200ffc0,	//   bdnz <flash32>
//<exit32>:
	0x00000000	//   .long 0x0
}

/* 16 bit flash ppc subroutine */
.fast16 AMD4
{
//<flash16>:
	0xa77c0002,	//   lhzu	 r27,2(r28)
	0xa75d0002,	//   lhzu	 r26,2(r29)
	0xb0410000,	//   sth r2,0(r1)
	0xb0830000,	//   sth r4,0(r3)
	0xb0c50000,	//   sth r6,0(r5)
	0xb37d0000,	//   sth r27,0(r29)
//<toggle16>:
	0x7f59d378,	//   mr  r25,r26
	0x7c0006ac,	//   eieio
	0xa35d0000,	//   lhz r26,0(r29)
	0x7c1bd040,	//   cmplw   r27,r26
	0x41820018,	//   beq <cont16>
	0x7f59ca79,	//   xor.	 r25,r26,r25
	0x4082ffe8,	//   bne <toggle16>
	0xa35d0000,	//   lhz r26,0(r29)
	0x7c1bd040,	//   cmplw   r27,r26
	0x40820008,	//   bne <exit16>
//<cont16>:
	0x4200ffc0,	// 	bdnz <flash16>
//<exit16>:
	0x00000000	// 	.long 0x0
}

/* 8 bit flash ppc subroutine */
.fast8 AMD4
{
//<flash8>:
	0x8f7c0001,	//   lbzu	 r27,1(r28)
	0x8f5d0001,	//   lbzu	 r26,1(r29)
	0x98410000,	//   stb r2,0(r1)
	0x98830000,	//   stb r4,0(r3)
	0x98c50000,	//   stb r6,0(r5)
	0x9b7d0000,	//   stb r27,0(r29)
//<toggle8>:
	0x7f59d378,	//   mr  r25,r26
	0x7c0006ac,	//   eieio
	0x8b5d0000,	//   lbz r26,0(r29)
	0x7c1bd040,	//   cmplw   r27,r26
	0x4182ff88,	//   beq <cont32>
	0x7f59ca79,	//   xor.	 r25,r26,r25
	0x4082ffe8,	//   bne <toggle8>
	0x8b5d0000,	//   lbz r26,0(r29)
	0x7c1bd040,	//   cmplw   r27,r26
	0x40820008,	//   bne <exit8>
//<cont8>:
	0x4200ffc0,	// 	bdnz <flash8>
//<exit8>:
	0x00000000 	// 	.long 0x0
}