processor_design

#! /usr/local/bin/vvp
:ivl_version "11.0 (stable)" "(v11_0-39-g83834959)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/local/lib/ivl/system.vpi";
:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/lib/ivl/va_math.vpi";
S_0x19f53e0 .scope module, "ProcTest_v" "ProcTest_v" 2 7;
 .timescale -9 -12;
v0x1ad1b60_0 .var "CLK", 0 0;
v0x1ad1c20_0 .var "Reset_L", 0 0;
v0x1ad1ce0_0 .net "WB_data", 63 0, v0x1ac8e10_0;  1 drivers
v0x1ad1db0_0 .net "currentPC", 63 0, v0x1ad0570_0;  1 drivers
v0x1ad1ea0_0 .net "first_instruction", 31 0, v0x1acf810_0;  1 drivers
v0x1ad1f90_0 .net "instruction", 31 0, v0x1ad08b0_0;  1 drivers
v0x1ad2030_0 .var "passed", 7 0;
v0x1ad20f0_0 .var "startPC", 63 0;
v0x1ad21e0_0 .var "watchdog", 15 0;
E_0x1a3a0c0 .event edge, v0x1ad21e0_0;
S_0x1a77c00 .scope task, "allPassed" "allPassed" 2 26, 2 26 0, S_0x19f53e0;
 .timescale -9 -12;
v0x1aa6b70_0 .var "numTests", 7 0;
v0x1aaa930_0 .var "passed", 7 0;
TD_ProcTest_v.allPassed ;
    %load/vec4 v0x1aaa930_0;
    %load/vec4 v0x1aa6b70_0;
    %cmp/e;
    %jmp/0xz  T_0.0, 4;
    %vpi_call 2 30 "$display", "All tests passed" {0 0 0};
    %jmp T_0.1;
T_0.0 ;
    %vpi_call 2 31 "$display", "Some tests failed: %d of %d passed", v0x1aaa930_0, v0x1aa6b70_0 {0 0 0};
T_0.1 ;
    %end;
S_0x1ac1620 .scope task, "passTest" "passTest" 2 17, 2 17 0, S_0x19f53e0;
 .timescale -9 -12;
v0x1aa5060_0 .var "actualOut", 63 0;
v0x1a91ef0_0 .var "expectedOut", 63 0;
v0x1ac1850_0 .var "passed", 7 0;
v0x1ac1910_0 .var "testType", 256 0;
TD_ProcTest_v.passTest ;
    %load/vec4 v0x1aa5060_0;
    %load/vec4 v0x1a91ef0_0;
    %cmp/e;
    %jmp/0xz  T_1.2, 4;
    %vpi_call 2 22 "$display", "%s passed", v0x1ac1910_0 {0 0 0};
    %load/vec4 v0x1ac1850_0;
    %addi 1, 0, 8;
    %store/vec4 v0x1ac1850_0, 0, 8;
    %jmp T_1.3;
T_1.2 ;
    %vpi_call 2 23 "$display", "%s failed: 0x%x should be 0x%x", v0x1ac1910_0, v0x1aa5060_0, v0x1a91ef0_0 {0 0 0};
T_1.3 ;
    %end;
S_0x1ac19f0 .scope module, "uut" "processor" 2 48, 3 15 0, S_0x19f53e0;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "resetl";
    .port_info 1 /INPUT 64 "startpc";
    .port_info 2 /OUTPUT 64 "currentpc";
    .port_info 3 /OUTPUT 64 "WB_data";
    .port_info 4 /OUTPUT 32 "instructionOut";
    .port_info 5 /OUTPUT 32 "IFID_instruction_debug";
    .port_info 6 /INPUT 1 "CLK";
v0x1acde00_0 .net "ALUB_in1_choice", 63 0, v0x1ac41c0_0;  1 drivers
v0x1acdf10_0 .net "ALUinA", 63 0, v0x1ac30e0_0;  1 drivers
v0x1ace020_0 .net "ALUinB", 63 0, v0x1ac3af0_0;  1 drivers
v0x1ace110_0 .net "BranchPC", 0 0, v0x1acbc60_0;  1 drivers
v0x1ace1b0_0 .net "CLK", 0 0, v0x1ad1b60_0;  1 drivers
v0x1ace3b0_0 .net "Control_Sel", 0 0, v0x1acd680_0;  1 drivers
v0x1ace450_0 .var "EXMEM_ALUout", 63 0;
v0x1ace4f0_0 .var "EXMEM_M", 3 0;
v0x1ace5b0_0 .var "EXMEM_PC", 63 0;
v0x1ace670_0 .var "EXMEM_WB", 1 0;
v0x1ace730_0 .var "EXMEM_WReg", 4 0;
v0x1ace7f0_0 .var "EXMEM_Zero", 0 0;
v0x1ace8c0_0 .var "EXMEM_rDataB", 63 0;
v0x1ace990_0 .net "ForwardA", 1 0, L_0x1ad3a20;  1 drivers
v0x1acea30_0 .net "ForwardB", 1 0, L_0x1ad4310;  1 drivers
v0x1aceb40_0 .var "IDEX_ALUfield", 10 0;
v0x1acec20_0 .var "IDEX_ALUop", 0 0;
v0x1acedd0_0 .var "IDEX_EX", 3 0;
v0x1acee70_0 .var "IDEX_M", 3 0;
v0x1acef30_0 .var "IDEX_PC", 63 0;
v0x1acf020_0 .var "IDEX_SignExtender", 63 0;
v0x1acf110_0 .var "IDEX_WB", 1 0;
v0x1acf1f0_0 .var "IDEX_WReg", 4 0;
v0x1acf2b0_0 .var "IDEX_rDataA", 63 0;
v0x1acf380_0 .var "IDEX_rDataB", 63 0;
v0x1acf450_0 .var "IDEX_rm", 4 0;
v0x1acf4f0_0 .var "IDEX_rn", 4 0;
v0x1acf5b0_0 .var "IFID_PC", 63 0;
v0x1acf6a0_0 .net "IFID_WriteEn", 0 0, v0x1acd220_0;  1 drivers
v0x1acf770_0 .var "IFID_instruction", 31 0;
v0x1acf810_0 .var "IFID_instruction_debug", 31 0;
v0x1acf8f0_0 .var "MEMWB_ALUout", 63 0;
v0x1acf9e0_0 .var "MEMWB_WB", 1 0;
v0x1acfcb0_0 .var "MEMWB_WReg", 4 0;
v0x1acfd70_0 .var "MEMWB_rData", 63 0;
v0x1acfe60_0 .net "PC_WriteEn", 0 0, v0x1acd5b0_0;  1 drivers
v0x1acff00_0 .net "WB_data", 63 0, v0x1ac8e10_0;  alias, 1 drivers
v0x1acffa0_0 .net *"_ivl_5", 0 0, L_0x1ad2430;  1 drivers
v0x1ad0080_0 .net *"_ivl_7", 4 0, L_0x1ad24d0;  1 drivers
v0x1ad0160_0 .net *"_ivl_9", 4 0, L_0x1ad2660;  1 drivers
v0x1ad0240_0 .net "aluctrl", 3 0, v0x1acc2b0_0;  1 drivers
v0x1ad0300_0 .net "aluout", 63 0, v0x1ac2190_0;  1 drivers
v0x1ad03d0_0 .net "alusrc", 0 0, v0x1acc3b0_0;  1 drivers
v0x1ad04a0_0 .net "branch", 0 0, v0x1acc470_0;  1 drivers
v0x1ad0570_0 .var "currentpc", 63 0;
v0x1ad0640_0 .net "dmemout", 63 0, v0x1ac4e40_0;  1 drivers
v0x1ad0710_0 .net "extimm", 63 0, v0x1acb560_0;  1 drivers
v0x1ad07e0_0 .net "instruction", 31 0, v0x1acdcc0_0;  1 drivers
v0x1ad08b0_0 .var "instructionOut", 31 0;
v0x1ad0950_0 .net "mem2reg", 0 0, v0x1acc510_0;  1 drivers
v0x1ad0a20_0 .net "memread", 0 0, v0x1acc5d0_0;  1 drivers
v0x1ad0af0_0 .net "memwrite", 0 0, v0x1acc6e0_0;  1 drivers
v0x1ad0bc0_0 .net "nextPC", 63 0, v0x1ac9570_0;  1 drivers
v0x1ad0c90_0 .net "opcode", 10 0, L_0x1ad28b0;  1 drivers
v0x1ad0d60_0 .net "rd", 4 0, L_0x1ad22a0;  1 drivers
v0x1ad0e30_0 .net "reg2loc", 0 0, v0x1acc880_0;  1 drivers
v0x1ad0f00_0 .net "regoutA", 63 0, L_0x1ae4d70;  1 drivers
v0x1ad0fd0_0 .net "regoutB", 63 0, L_0x1ae53f0;  1 drivers
v0x1ad10a0_0 .net "regwrite", 0 0, v0x1acc940_0;  1 drivers
v0x1ad1170_0 .net "resetl", 0 0, v0x1ad1c20_0;  1 drivers
v0x1ad1210_0 .net "rm", 4 0, L_0x1ad2340;  1 drivers
v0x1ad12b0_0 .net "rn", 4 0, L_0x1ad2730;  1 drivers
v0x1ad13a0_0 .net "signop", 2 0, v0x1acca00_0;  1 drivers
v0x1ad1490_0 .net "startpc", 63 0, v0x1ad20f0_0;  1 drivers
v0x1ad1530_0 .net "uncond_branch", 0 0, v0x1accac0_0;  1 drivers
v0x1ad19e0_0 .net "zero", 0 0, L_0x1ae5be0;  1 drivers
L_0x1ad22a0 .part v0x1acf770_0, 0, 5;
L_0x1ad2340 .part v0x1acf770_0, 5, 5;
L_0x1ad2430 .part v0x1acf770_0, 28, 1;
L_0x1ad24d0 .part v0x1acf770_0, 0, 5;
L_0x1ad2660 .part v0x1acf770_0, 16, 5;
L_0x1ad2730 .functor MUXZ 5, L_0x1ad2660, L_0x1ad24d0, L_0x1ad2430, C4<>;
L_0x1ad28b0 .part v0x1acf770_0, 21, 11;
L_0x1ad46e0 .part v0x1ace670_0, 0, 1;
L_0x1ad47d0 .part v0x1acf9e0_0, 0, 1;
L_0x1ad4870 .part v0x1acee70_0, 0, 1;
L_0x1ae55e0 .part v0x1acf9e0_0, 0, 1;
L_0x1ae5770 .part v0x1acf770_0, 0, 26;
L_0x1ae5dc0 .part v0x1acf9e0_0, 1, 1;
L_0x1ae5e60 .part v0x1ace4f0_0, 0, 1;
L_0x1ae5f80 .part v0x1ace4f0_0, 1, 1;
L_0x1ae6070 .part v0x1ace4f0_0, 2, 1;
L_0x1ae61a0 .part v0x1ace4f0_0, 3, 1;
S_0x1ac1c30 .scope module, "ALU" "ALU" 3 243, 4 10 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "BusW";
    .port_info 1 /OUTPUT 1 "Zero";
    .port_info 2 /INPUT 64 "BusA";
    .port_info 3 /INPUT 64 "BusB";
    .port_info 4 /INPUT 4 "ALUCtrl";
    .port_info 5 /INPUT 1 "Clk";
v0x1ac1ef0_0 .net "ALUCtrl", 3 0, v0x1acedd0_0;  1 drivers
v0x1ac1ff0_0 .net "BusA", 63 0, v0x1ac30e0_0;  alias, 1 drivers
v0x1ac20d0_0 .net "BusB", 63 0, v0x1ac3af0_0;  alias, 1 drivers
v0x1ac2190_0 .var "BusW", 63 0;
v0x1ac2270_0 .net "Clk", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1ac2380_0 .net "Zero", 0 0, L_0x1ae5be0;  alias, 1 drivers
L_0x7f8a2d7662e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x1ac2440_0 .net/2u *"_ivl_0", 63 0, L_0x7f8a2d7662e8;  1 drivers
v0x1ac2520_0 .net *"_ivl_2", 0 0, L_0x1ae5960;  1 drivers
L_0x7f8a2d766330 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v0x1ac25e0_0 .net/2s *"_ivl_4", 1 0, L_0x7f8a2d766330;  1 drivers
L_0x7f8a2d766378 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x1ac26c0_0 .net/2s *"_ivl_6", 1 0, L_0x7f8a2d766378;  1 drivers
v0x1ac27a0_0 .net *"_ivl_8", 1 0, L_0x1ae5a50;  1 drivers
E_0x1a39d60 .event edge, v0x1ac1ef0_0, v0x1ac20d0_0, v0x1ac1ff0_0;
L_0x1ae5960 .cmp/eq 64, v0x1ac2190_0, L_0x7f8a2d7662e8;
L_0x1ae5a50 .functor MUXZ 2, L_0x7f8a2d766378, L_0x7f8a2d766330, L_0x1ae5960, C4<>;
L_0x1ae5be0 .delay 1 (1000,1000,1000) L_0x1ae5be0/d;
L_0x1ae5be0/d .part L_0x1ae5a50, 0, 1;
S_0x1ac2940 .scope module, "ALUA" "Mux3to1" 3 239, 5 1 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "out";
    .port_info 1 /INPUT 64 "in1";
    .port_info 2 /INPUT 64 "in2";
    .port_info 3 /INPUT 64 "in3";
    .port_info 4 /INPUT 2 "ctrl";
    .port_info 5 /INPUT 1 "Clk";
    .port_info 6 /INPUT 1 "en";
v0x1ac2bd0_0 .net "Clk", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1ac2c90_0 .net "ctrl", 1 0, L_0x1ad3a20;  alias, 1 drivers
L_0x7f8a2d7662a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x1ac2d50_0 .net "en", 0 0, L_0x7f8a2d7662a0;  1 drivers
v0x1ac2df0_0 .net "in1", 63 0, v0x1acf2b0_0;  1 drivers
v0x1ac2ed0_0 .net "in2", 63 0, v0x1ac8e10_0;  alias, 1 drivers
v0x1ac3000_0 .net "in3", 63 0, v0x1ace450_0;  1 drivers
v0x1ac30e0_0 .var "out", 63 0;
E_0x1aacba0 .event edge, v0x1ac2c90_0, v0x1ac2df0_0, v0x1ac2ed0_0, v0x1ac3000_0;
S_0x1ac32a0 .scope module, "ALUB" "Mux3to1" 3 235, 5 1 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "out";
    .port_info 1 /INPUT 64 "in1";
    .port_info 2 /INPUT 64 "in2";
    .port_info 3 /INPUT 64 "in3";
    .port_info 4 /INPUT 2 "ctrl";
    .port_info 5 /INPUT 1 "Clk";
    .port_info 6 /INPUT 1 "en";
v0x1ac35a0_0 .net "Clk", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1ac36b0_0 .net "ctrl", 1 0, L_0x1ad4310;  alias, 1 drivers
L_0x7f8a2d766258 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v0x1ac3790_0 .net "en", 0 0, L_0x7f8a2d766258;  1 drivers
v0x1ac3830_0 .net "in1", 63 0, v0x1ac41c0_0;  alias, 1 drivers
v0x1ac3910_0 .net "in2", 63 0, v0x1ac8e10_0;  alias, 1 drivers
v0x1ac3a20_0 .net "in3", 63 0, v0x1ace450_0;  alias, 1 drivers
v0x1ac3af0_0 .var "out", 63 0;
E_0x1ac3530 .event edge, v0x1ac36b0_0, v0x1ac3830_0, v0x1ac2ed0_0, v0x1ac3000_0;
S_0x1ac3cc0 .scope module, "ALUB_in1_src" "Mux2to1" 3 231, 6 1 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "out";
    .port_info 1 /INPUT 64 "in1";
    .port_info 2 /INPUT 64 "in2";
    .port_info 3 /INPUT 1 "ctrl";
v0x1ac3f10_0 .net "ctrl", 0 0, v0x1acec20_0;  1 drivers
v0x1ac3ff0_0 .net "in1", 63 0, v0x1acf380_0;  1 drivers
v0x1ac40d0_0 .net "in2", 63 0, v0x1acf020_0;  1 drivers
v0x1ac41c0_0 .var "out", 63 0;
E_0x1a3a250 .event edge, v0x1ac3f10_0, v0x1ac3ff0_0, v0x1ac40d0_0;
S_0x1ac4340 .scope module, "DataMemory" "DataMemory" 3 251, 7 5 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "ReadData";
    .port_info 1 /INPUT 64 "Address";
    .port_info 2 /INPUT 64 "WriteData";
    .port_info 3 /INPUT 1 "MemoryRead";
    .port_info 4 /INPUT 1 "MemoryWrite";
    .port_info 5 /INPUT 1 "Clock";
v0x1ac4b10_0 .net "Address", 63 0, v0x1ace450_0;  alias, 1 drivers
v0x1ac4c40_0 .net "Clock", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1ac4d00_0 .net "MemoryRead", 0 0, L_0x1ae5e60;  1 drivers
v0x1ac4da0_0 .net "MemoryWrite", 0 0, L_0x1ae5f80;  1 drivers
v0x1ac4e40_0 .var "ReadData", 63 0;
v0x1ac4f70_0 .net "WriteData", 63 0, v0x1ace8c0_0;  1 drivers
v0x1ac5050 .array "memBank", 0 1023, 7 0;
E_0x1ac4650 .event posedge, v0x1ac2270_0;
E_0x1ac46d0/0 .event edge, v0x1ac4d00_0, v0x1ac3000_0;
E_0x1ac46d0/1 .event posedge, v0x1ac2270_0;
E_0x1ac46d0 .event/or E_0x1ac46d0/0, E_0x1ac46d0/1;
S_0x1ac4730 .scope task, "initset" "initset" 7 16, 7 16 0, S_0x1ac4340;
 .timescale -9 -12;
v0x1ac4930_0 .var "addr", 63 0;
v0x1ac4a30_0 .var "data", 63 0;
TD_ProcTest_v.uut.DataMemory.initset ;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 56, 7;
    %ix/getv 4, v0x1ac4930_0;
    %store/vec4a v0x1ac5050, 4, 0;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 48, 7;
    %load/vec4 v0x1ac4930_0;
    %pad/u 65;
    %addi 1, 0, 65;
    %ix/vec4 4;
    %store/vec4a v0x1ac5050, 4, 0;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 40, 7;
    %load/vec4 v0x1ac4930_0;
    %pad/u 65;
    %addi 2, 0, 65;
    %ix/vec4 4;
    %store/vec4a v0x1ac5050, 4, 0;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 32, 7;
    %load/vec4 v0x1ac4930_0;
    %pad/u 65;
    %addi 3, 0, 65;
    %ix/vec4 4;
    %store/vec4a v0x1ac5050, 4, 0;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 24, 6;
    %load/vec4 v0x1ac4930_0;
    %pad/u 65;
    %addi 4, 0, 65;
    %ix/vec4 4;
    %store/vec4a v0x1ac5050, 4, 0;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 16, 6;
    %load/vec4 v0x1ac4930_0;
    %pad/u 65;
    %addi 5, 0, 65;
    %ix/vec4 4;
    %store/vec4a v0x1ac5050, 4, 0;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 8, 5;
    %load/vec4 v0x1ac4930_0;
    %pad/u 65;
    %addi 6, 0, 65;
    %ix/vec4 4;
    %store/vec4a v0x1ac5050, 4, 0;
    %load/vec4 v0x1ac4a30_0;
    %parti/s 8, 0, 2;
    %load/vec4 v0x1ac4930_0;
    %pad/u 65;
    %addi 7, 0, 65;
    %ix/vec4 4;
    %store/vec4a v0x1ac5050, 4, 0;
    %end;
S_0x1ac5210 .scope module, "FU" "ForwardingUnit" 3 183, 8 3 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 2 "ForwardA";
    .port_info 1 /OUTPUT 2 "ForwardB";
    .port_info 2 /INPUT 1 "EXMEM_RegWrite";
    .port_info 3 /INPUT 1 "MEMWB_RegWrite";
    .port_info 4 /INPUT 5 "EXMEM_WriteRegister";
    .port_info 5 /INPUT 5 "MEMWB_WriteRegister";
    .port_info 6 /INPUT 5 "IDEX_rm";
    .port_info 7 /INPUT 5 "IDEX_rn";
    .port_info 8 /INPUT 1 "Clk";
L_0x1a91800/0/0 .functor OR 1, L_0x1ad29d0, L_0x1ad2b50, L_0x1ad2bf0, L_0x1ad2ce0;
L_0x1a91800/0/4 .functor OR 1, L_0x1ad2e00, C4<0>, C4<0>, C4<0>;
L_0x1a91800 .functor OR 1, L_0x1a91800/0/0, L_0x1a91800/0/4, C4<0>, C4<0>;
L_0x1ad2ef0 .functor AND 1, L_0x1ad46e0, L_0x1a91800, v0x1ac59b0_0, C4<1>;
L_0x1ad3000/0/0 .functor OR 1, L_0x1ad3110, L_0x1ad3240, L_0x1ad3330, L_0x1ad3470;
L_0x1ad3000/0/4 .functor OR 1, L_0x1ad3670, C4<0>, C4<0>, C4<0>;
L_0x1ad3000 .functor OR 1, L_0x1ad3000/0/0, L_0x1ad3000/0/4, C4<0>, C4<0>;
L_0x1ad37c0 .functor AND 1, L_0x1ad47d0, L_0x1ad3000, v0x1ac64f0_0, C4<1>;
L_0x1ad38b0 .functor BUFZ 1, L_0x1ad2ef0, C4<0>, C4<0>, C4<0>;
L_0x1ad3970 .functor NOT 1, L_0x1ad2ef0, C4<0>, C4<0>, C4<0>;
L_0x1ad3b10 .functor AND 1, L_0x1ad3970, L_0x1ad37c0, C4<1>, C4<1>;
L_0x1ad3c70/d .functor AND 1, L_0x1ad46e0, L_0x1a91800, v0x1ac5f20_0, C4<1>;
L_0x1ad3c70 .delay 1 (50000,50000,50000) L_0x1ad3c70/d;
L_0x1ad3f80/d .functor AND 1, L_0x1ad47d0, L_0x1ad3000, v0x1ac6ab0_0, C4<1>;
L_0x1ad3f80 .delay 1 (50000,50000,50000) L_0x1ad3f80/d;
L_0x1ad4130 .functor BUFZ 1, L_0x1ad3c70, C4<0>, C4<0>, C4<0>;
L_0x1ad4250/d .functor NOT 1, L_0x1ad3c70, C4<0>, C4<0>, C4<0>;
L_0x1ad4250 .delay 1 (50000,50000,50000) L_0x1ad4250/d;
L_0x1ad4470/d .functor AND 1, L_0x1ad4250, L_0x1ad3f80, C4<1>, C4<1>;
L_0x1ad4470 .delay 1 (50000,50000,50000) L_0x1ad4470/d;
v0x1ac6be0_0 .net "Clk", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1ac6c80_0 .net "EXMEM_RegWrite", 0 0, L_0x1ad46e0;  1 drivers
v0x1ac6d40_0 .net "EXMEM_WriteRegister", 4 0, v0x1ace730_0;  1 drivers
v0x1ac6e10_0 .net "ForwardA", 1 0, L_0x1ad3a20;  alias, 1 drivers
v0x1ac6ed0_0 .net "ForwardB", 1 0, L_0x1ad4310;  alias, 1 drivers
v0x1ac6fc0_0 .net "IDEX_rm", 4 0, v0x1acf450_0;  1 drivers
v0x1ac70b0_0 .net "IDEX_rn", 4 0, v0x1acf4f0_0;  1 drivers
v0x1ac71c0_0 .net "MEMWB_RegWrite", 0 0, L_0x1ad47d0;  1 drivers
v0x1ac7280_0 .net "MEMWB_WriteRegister", 4 0, v0x1acfcb0_0;  1 drivers
v0x1ac7340_0 .net *"_ivl_1", 0 0, L_0x1ad29d0;  1 drivers
v0x1ac7420_0 .net *"_ivl_11", 0 0, L_0x1ad3110;  1 drivers
v0x1ac7500_0 .net *"_ivl_13", 0 0, L_0x1ad3240;  1 drivers
v0x1ac75e0_0 .net *"_ivl_15", 0 0, L_0x1ad3330;  1 drivers
v0x1ac76c0_0 .net *"_ivl_17", 0 0, L_0x1ad3470;  1 drivers
v0x1ac77a0_0 .net *"_ivl_19", 0 0, L_0x1ad3670;  1 drivers
v0x1ac7880_0 .net *"_ivl_23", 0 0, L_0x1ad38b0;  1 drivers
v0x1ac7960_0 .net *"_ivl_24", 0 0, L_0x1ad3b10;  1 drivers
v0x1ac7a40_0 .net *"_ivl_3", 0 0, L_0x1ad2b50;  1 drivers
v0x1ac7b20_0 .net *"_ivl_30", 0 0, L_0x1ad4130;  1 drivers
v0x1ac7c00_0 .net *"_ivl_31", 0 0, L_0x1ad4470;  1 drivers
v0x1ac7ce0_0 .net *"_ivl_5", 0 0, L_0x1ad2bf0;  1 drivers
v0x1ac7dc0_0 .net *"_ivl_7", 0 0, L_0x1ad2ce0;  1 drivers
v0x1ac7ea0_0 .net *"_ivl_9", 0 0, L_0x1ad2e00;  1 drivers
v0x1ac7f80_0 .net "a", 0 0, L_0x1a91800;  1 drivers
v0x1ac8040_0 .net "b", 0 0, v0x1ac59b0_0;  1 drivers
v0x1ac80e0_0 .net "b1", 0 0, v0x1ac5f20_0;  1 drivers
v0x1ac8180_0 .net "c", 0 0, L_0x1ad3000;  1 drivers
v0x1ac8220_0 .net "d", 0 0, v0x1ac64f0_0;  1 drivers
v0x1ac82c0_0 .net "d1", 0 0, v0x1ac6ab0_0;  1 drivers
v0x1ac8390_0 .net "notx", 0 0, L_0x1ad3970;  1 drivers
v0x1ac8430_0 .net "notx1", 0 0, L_0x1ad4250;  1 drivers
v0x1ac84d0_0 .net "x", 0 0, L_0x1ad2ef0;  1 drivers
v0x1ac8570_0 .net "x1", 0 0, L_0x1ad3c70;  1 drivers
v0x1ac8630_0 .net "y", 0 0, L_0x1ad37c0;  1 drivers
v0x1ac86f0_0 .net "y1", 0 0, L_0x1ad3f80;  1 drivers
L_0x1ad29d0 .part v0x1ace730_0, 4, 1;
L_0x1ad2b50 .part v0x1ace730_0, 3, 1;
L_0x1ad2bf0 .part v0x1ace730_0, 2, 1;
L_0x1ad2ce0 .part v0x1ace730_0, 1, 1;
L_0x1ad2e00 .part v0x1ace730_0, 0, 1;
L_0x1ad3110 .part v0x1acfcb0_0, 4, 1;
L_0x1ad3240 .part v0x1acfcb0_0, 3, 1;
L_0x1ad3330 .part v0x1acfcb0_0, 2, 1;
L_0x1ad3470 .part v0x1acfcb0_0, 1, 1;
L_0x1ad3670 .part v0x1acfcb0_0, 0, 1;
L_0x1ad3a20 .concat8 [ 1 1 0 0], L_0x1ad3b10, L_0x1ad38b0;
L_0x1ad4310 .concat8 [ 1 1 0 0], L_0x1ad4470, L_0x1ad4130;
S_0x1ac5520 .scope module, "CompMEM_WriteReg_EXrs" "CompareAddress" 8 11, 8 41 0, S_0x1ac5210;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 1 "out";
    .port_info 1 /INPUT 5 "in1";
    .port_info 2 /INPUT 5 "in2";
v0x1ac57d0_0 .net "in1", 4 0, v0x1ace730_0;  alias, 1 drivers
v0x1ac58d0_0 .net "in2", 4 0, v0x1acf450_0;  alias, 1 drivers
v0x1ac59b0_0 .var "out", 0 0;
E_0x1ac4570 .event edge, v0x1ac57d0_0, v0x1ac58d0_0;
S_0x1ac5ad0 .scope module, "CompMEM_WriteReg_EXrt" "CompareAddress" 8 28, 8 41 0, S_0x1ac5210;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 1 "out";
    .port_info 1 /INPUT 5 "in1";
    .port_info 2 /INPUT 5 "in2";
v0x1ac5d80_0 .net "in1", 4 0, v0x1ace730_0;  alias, 1 drivers
v0x1ac5e60_0 .net "in2", 4 0, v0x1acf4f0_0;  alias, 1 drivers
v0x1ac5f20_0 .var "out", 0 0;
E_0x1ac5d00 .event edge, v0x1ac57d0_0, v0x1ac5e60_0;
S_0x1ac6040 .scope module, "CompWB_WriteReg_EXrs" "CompareAddress" 8 17, 8 41 0, S_0x1ac5210;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 1 "out";
    .port_info 1 /INPUT 5 "in1";
    .port_info 2 /INPUT 5 "in2";
v0x1ac6300_0 .net "in1", 4 0, v0x1acfcb0_0;  alias, 1 drivers
v0x1ac6400_0 .net "in2", 4 0, v0x1acf450_0;  alias, 1 drivers
v0x1ac64f0_0 .var "out", 0 0;
E_0x1ac62a0 .event edge, v0x1ac6300_0, v0x1ac58d0_0;
S_0x1ac6620 .scope module, "CompWB_WriteReg_EXrt" "CompareAddress" 8 30, 8 41 0, S_0x1ac5210;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 1 "out";
    .port_info 1 /INPUT 5 "in1";
    .port_info 2 /INPUT 5 "in2";
v0x1ac68d0_0 .net "in1", 4 0, v0x1acfcb0_0;  alias, 1 drivers
v0x1ac69e0_0 .net "in2", 4 0, v0x1acf4f0_0;  alias, 1 drivers
v0x1ac6ab0_0 .var "out", 0 0;
E_0x1ac6850 .event edge, v0x1ac6300_0, v0x1ac5e60_0;
S_0x1ac8920 .scope module, "Memory_WB_Mux" "Mux2to1" 3 247, 6 1 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "out";
    .port_info 1 /INPUT 64 "in1";
    .port_info 2 /INPUT 64 "in2";
    .port_info 3 /INPUT 1 "ctrl";
v0x1ac8b60_0 .net "ctrl", 0 0, L_0x1ae5dc0;  1 drivers
v0x1ac8c40_0 .net "in1", 63 0, v0x1acf8f0_0;  1 drivers
v0x1ac8d20_0 .net "in2", 63 0, v0x1acfd70_0;  1 drivers
v0x1ac8e10_0 .var "out", 63 0;
E_0x1ac8ae0 .event edge, v0x1ac8b60_0, v0x1ac8c40_0, v0x1ac8d20_0;
S_0x1ac8fa0 .scope module, "PCLogic" "PCLogic" 3 261, 9 3 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "NextPC";
    .port_info 1 /INPUT 64 "CurrPC";
    .port_info 2 /INPUT 64 "SignExtImm64";
    .port_info 3 /INPUT 1 "Branch";
    .port_info 4 /INPUT 1 "ALUZero";
    .port_info 5 /INPUT 1 "Unconditional";
    .port_info 6 /INPUT 1 "WriteEn";
v0x1ac9310_0 .net "ALUZero", 0 0, v0x1ace7f0_0;  1 drivers
v0x1ac93f0_0 .net "Branch", 0 0, L_0x1ae6070;  1 drivers
v0x1ac94b0_0 .net "CurrPC", 63 0, v0x1acf5b0_0;  1 drivers
v0x1ac9570_0 .var "NextPC", 63 0;
v0x1ac9650_0 .net "SignExtImm64", 63 0, v0x1ace5b0_0;  1 drivers
v0x1ac9780_0 .net "Unconditional", 0 0, L_0x1ae61a0;  1 drivers
v0x1ac9840_0 .net "WriteEn", 0 0, v0x1acd5b0_0;  alias, 1 drivers
E_0x1ac9270/0 .event edge, v0x1ac9840_0, v0x1ac93f0_0, v0x1ac9310_0, v0x1ac9780_0;
E_0x1ac9270/1 .event edge, v0x1ac9650_0, v0x1ac94b0_0;
E_0x1ac9270 .event/or E_0x1ac9270/0, E_0x1ac9270/1;
S_0x1ac9a20 .scope module, "RegisterFile" "RegisterFile" 3 221, 10 3 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "BusA";
    .port_info 1 /OUTPUT 64 "BusB";
    .port_info 2 /INPUT 64 "BusW";
    .port_info 3 /INPUT 5 "RA";
    .port_info 4 /INPUT 5 "RB";
    .port_info 5 /INPUT 5 "RW";
    .port_info 6 /INPUT 1 "RegWr";
    .port_info 7 /INPUT 1 "Clk";
v0x1ac9c40_0 .net "BusA", 63 0, L_0x1ae4d70;  alias, 1 drivers
v0x1ac9d40_0 .net "BusB", 63 0, L_0x1ae53f0;  alias, 1 drivers
v0x1ac9e20_0 .net "BusW", 63 0, v0x1ac8e10_0;  alias, 1 drivers
v0x1ac9ec0_0 .net "Clk", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1ac9f60_0 .net "RA", 4 0, L_0x1ad2340;  alias, 1 drivers
v0x1aca090_0 .net "RB", 4 0, L_0x1ad2730;  alias, 1 drivers
v0x1aca170_0 .net "RW", 4 0, v0x1acfcb0_0;  alias, 1 drivers
v0x1aca230_0 .net "RegWr", 0 0, L_0x1ae55e0;  1 drivers
v0x1aca2f0_0 .net *"_ivl_0", 31 0, L_0x1ad4970;  1 drivers
v0x1aca3d0_0 .net *"_ivl_10", 63 0, L_0x1ae4b60;  1 drivers
v0x1aca4b0_0 .net *"_ivl_12", 6 0, L_0x1ae4c00;  1 drivers
L_0x7f8a2d7660f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x1aca590_0 .net *"_ivl_15", 1 0, L_0x7f8a2d7660f0;  1 drivers
v0x1aca670_0 .net *"_ivl_18", 31 0, L_0x1ae4f50;  1 drivers
L_0x7f8a2d766138 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x1aca750_0 .net *"_ivl_21", 26 0, L_0x7f8a2d766138;  1 drivers
L_0x7f8a2d766180 .functor BUFT 1, C4<00000000000000000000000000011111>, C4<0>, C4<0>, C4<0>;
v0x1aca830_0 .net/2u *"_ivl_22", 31 0, L_0x7f8a2d766180;  1 drivers
v0x1aca910_0 .net *"_ivl_24", 0 0, L_0x1ae5080;  1 drivers
L_0x7f8a2d7661c8 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x1aca9d0_0 .net/2u *"_ivl_26", 63 0, L_0x7f8a2d7661c8;  1 drivers
v0x1acaab0_0 .net *"_ivl_28", 63 0, L_0x1ae51c0;  1 drivers
L_0x7f8a2d766018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x1acab90_0 .net *"_ivl_3", 26 0, L_0x7f8a2d766018;  1 drivers
v0x1acac70_0 .net *"_ivl_30", 6 0, L_0x1ae52b0;  1 drivers
L_0x7f8a2d766210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x1acad50_0 .net *"_ivl_33", 1 0, L_0x7f8a2d766210;  1 drivers
L_0x7f8a2d766060 .functor BUFT 1, C4<00000000000000000000000000011111>, C4<0>, C4<0>, C4<0>;
v0x1acae30_0 .net/2u *"_ivl_4", 31 0, L_0x7f8a2d766060;  1 drivers
v0x1acaf10_0 .net *"_ivl_6", 0 0, L_0x1ae4a20;  1 drivers
L_0x7f8a2d7660a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x1acafd0_0 .net/2u *"_ivl_8", 63 0, L_0x7f8a2d7660a8;  1 drivers
v0x1acb0b0_0 .var/i "i", 31 0;
v0x1acb190 .array "registers", 0 31, 63 0;
E_0x1ac9180 .event negedge, v0x1ac2270_0;
L_0x1ad4970 .concat [ 5 27 0 0], L_0x1ad2340, L_0x7f8a2d766018;
L_0x1ae4a20 .cmp/eq 32, L_0x1ad4970, L_0x7f8a2d766060;
L_0x1ae4b60 .array/port v0x1acb190, L_0x1ae4c00;
L_0x1ae4c00 .concat [ 5 2 0 0], L_0x1ad2340, L_0x7f8a2d7660f0;
L_0x1ae4d70 .functor MUXZ 64, L_0x1ae4b60, L_0x7f8a2d7660a8, L_0x1ae4a20, C4<>;
L_0x1ae4f50 .concat [ 5 27 0 0], L_0x1ad2730, L_0x7f8a2d766138;
L_0x1ae5080 .cmp/eq 32, L_0x1ae4f50, L_0x7f8a2d766180;
L_0x1ae51c0 .array/port v0x1acb190, L_0x1ae52b0;
L_0x1ae52b0 .concat [ 5 2 0 0], L_0x1ad2730, L_0x7f8a2d766210;
L_0x1ae53f0 .functor MUXZ 64, L_0x1ae51c0, L_0x7f8a2d7661c8, L_0x1ae5080, C4<>;
S_0x1acb350 .scope module, "SignExtender" "SignExtender" 3 227, 11 3 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 64 "BusImm";
    .port_info 1 /INPUT 26 "Imm26";
    .port_info 2 /INPUT 3 "Ctrl";
    .port_info 3 /INPUT 1 "Clk";
v0x1acb560_0 .var "BusImm", 63 0;
v0x1acb660_0 .net "Clk", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1acb720_0 .net "Ctrl", 2 0, v0x1acca00_0;  alias, 1 drivers
v0x1acb7f0_0 .net "Imm26", 25 0, L_0x1ae5770;  1 drivers
v0x1acb8d0_0 .net "shift", 1 0, L_0x1ae56d0;  1 drivers
E_0x1acb4e0 .event edge, v0x1ac2270_0;
L_0x1ae56d0 .part L_0x1ae5770, 21, 2;
S_0x1acba80 .scope module, "branchPC" "BranchPC" 3 257, 9 18 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 1 "BranchPC";
    .port_info 1 /INPUT 64 "ExtendedImm";
    .port_info 2 /INPUT 64 "CurrentPC";
    .port_info 3 /INPUT 1 "Clk";
v0x1acbc60_0 .var "BranchPC", 0 0;
v0x1acbd40_0 .net "Clk", 0 0, v0x1ad1b60_0;  alias, 1 drivers
v0x1acbe00_0 .net "CurrentPC", 63 0, v0x1acef30_0;  1 drivers
v0x1acbed0_0 .net "ExtendedImm", 63 0, v0x1acf020_0;  alias, 1 drivers
S_0x1acc050 .scope module, "control" "control" 3 207, 12 19 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 1 "reg2loc";
    .port_info 1 /OUTPUT 1 "alusrc";
    .port_info 2 /OUTPUT 1 "mem2reg";
    .port_info 3 /OUTPUT 1 "regwrite";
    .port_info 4 /OUTPUT 1 "memread";
    .port_info 5 /OUTPUT 1 "memwrite";
    .port_info 6 /OUTPUT 1 "branch";
    .port_info 7 /OUTPUT 1 "uncond_branch";
    .port_info 8 /OUTPUT 4 "aluop";
    .port_info 9 /OUTPUT 3 "signop";
    .port_info 10 /INPUT 11 "opcode";
v0x1acc2b0_0 .var "aluop", 3 0;
v0x1acc3b0_0 .var "alusrc", 0 0;
v0x1acc470_0 .var "branch", 0 0;
v0x1acc510_0 .var "mem2reg", 0 0;
v0x1acc5d0_0 .var "memread", 0 0;
v0x1acc6e0_0 .var "memwrite", 0 0;
v0x1acc7a0_0 .net "opcode", 10 0, L_0x1ad28b0;  alias, 1 drivers
v0x1acc880_0 .var "reg2loc", 0 0;
v0x1acc940_0 .var "regwrite", 0 0;
v0x1acca00_0 .var "signop", 2 0;
v0x1accac0_0 .var "uncond_branch", 0 0;
E_0x1acc230 .event edge, v0x1acc7a0_0;
S_0x1accd20 .scope module, "hdu" "HazardDetectionUnit" 3 195, 13 3 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 1 "PC_WriteEn";
    .port_info 1 /OUTPUT 1 "IFID_WriteEn";
    .port_info 2 /OUTPUT 1 "Stall_flush";
    .port_info 3 /INPUT 1 "IDEX_MemRead";
    .port_info 4 /INPUT 5 "IDEX_rd";
    .port_info 5 /INPUT 5 "IFID_rn";
    .port_info 6 /INPUT 5 "IFID_rm";
    .port_info 7 /INPUT 5 "IFID_rd";
v0x1acd060_0 .net "IDEX_MemRead", 0 0, L_0x1ad4870;  1 drivers
v0x1acd140_0 .net "IDEX_rd", 4 0, v0x1acf1f0_0;  1 drivers
v0x1acd220_0 .var "IFID_WriteEn", 0 0;
v0x1acd2f0_0 .net "IFID_rd", 4 0, L_0x1ad22a0;  alias, 1 drivers
v0x1acd3d0_0 .net "IFID_rm", 4 0, L_0x1ad2340;  alias, 1 drivers
v0x1acd4e0_0 .net "IFID_rn", 4 0, L_0x1ad2730;  alias, 1 drivers
v0x1acd5b0_0 .var "PC_WriteEn", 0 0;
v0x1acd680_0 .var "Stall_flush", 0 0;
E_0x1accfd0 .event edge, v0x1aca090_0, v0x1ac9f60_0, v0x1acd140_0, v0x1acd060_0;
S_0x1acd850 .scope module, "imem" "InstructionMemory" 3 202, 14 3 0, S_0x1ac19f0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 32 "Data";
    .port_info 1 /INPUT 64 "Address";
P_0x1aa82e0 .param/l "MemSize" 0 14 5, +C4<00000000000000000000000000101000>;
P_0x1aa8320 .param/l "T_rd" 0 14 4, +C4<00000000000000000000000000010100>;
v0x1acdbc0_0 .net "Address", 63 0, v0x1ad0570_0;  alias, 1 drivers
v0x1acdcc0_0 .var "Data", 31 0;
E_0x1acdb40 .event edge, v0x1acdbc0_0;
    .scope S_0x1ac5520;
T_3 ;
    %wait E_0x1ac4570;
    %load/vec4 v0x1ac57d0_0;
    %pad/u 32;
    %load/vec4 v0x1ac58d0_0;
    %pad/u 32;
    %sub;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_3.0, 4;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1ac59b0_0, 0;
    %jmp T_3.1;
T_3.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1ac59b0_0, 0;
T_3.1 ;
    %jmp T_3;
    .thread T_3, $push;
    .scope S_0x1ac6040;
T_4 ;
    %wait E_0x1ac62a0;
    %load/vec4 v0x1ac6300_0;
    %pad/u 32;
    %load/vec4 v0x1ac6400_0;
    %pad/u 32;
    %sub;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_4.0, 4;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1ac64f0_0, 0;
    %jmp T_4.1;
T_4.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1ac64f0_0, 0;
T_4.1 ;
    %jmp T_4;
    .thread T_4, $push;
    .scope S_0x1ac5ad0;
T_5 ;
    %wait E_0x1ac5d00;
    %load/vec4 v0x1ac5d80_0;
    %pad/u 32;
    %load/vec4 v0x1ac5e60_0;
    %pad/u 32;
    %sub;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_5.0, 4;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1ac5f20_0, 0;
    %jmp T_5.1;
T_5.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1ac5f20_0, 0;
T_5.1 ;
    %jmp T_5;
    .thread T_5, $push;
    .scope S_0x1ac6620;
T_6 ;
    %wait E_0x1ac6850;
    %load/vec4 v0x1ac68d0_0;
    %pad/u 32;
    %load/vec4 v0x1ac69e0_0;
    %pad/u 32;
    %sub;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_6.0, 4;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1ac6ab0_0, 0;
    %jmp T_6.1;
T_6.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1ac6ab0_0, 0;
T_6.1 ;
    %jmp T_6;
    .thread T_6, $push;
    .scope S_0x1accd20;
T_7 ;
    %wait E_0x1accfd0;
    %load/vec4 v0x1acd060_0;
    %load/vec4 v0x1acd140_0;
    %load/vec4 v0x1acd4e0_0;
    %cmp/e;
    %flag_get/vec4 4;
    %load/vec4 v0x1acd140_0;
    %load/vec4 v0x1acd3d0_0;
    %cmp/e;
    %flag_get/vec4 4;
    %or;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_7.0, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x1acd5b0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x1acd220_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x1acd680_0, 0, 1;
    %jmp T_7.1;
T_7.0 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x1acd5b0_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x1acd220_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x1acd680_0, 0, 1;
T_7.1 ;
    %jmp T_7;
    .thread T_7, $push;
    .scope S_0x1acd850;
T_8 ;
    %wait E_0x1acdb40;
    %load/vec4 v0x1acdbc0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 64;
    %cmp/u;
    %jmp/1 T_8.0, 6;
    %dup/vec4;
    %pushi/vec4 4, 0, 64;
    %cmp/u;
    %jmp/1 T_8.1, 6;
    %dup/vec4;
    %pushi/vec4 8, 0, 64;
    %cmp/u;
    %jmp/1 T_8.2, 6;
    %dup/vec4;
    %pushi/vec4 12, 0, 64;
    %cmp/u;
    %jmp/1 T_8.3, 6;
    %dup/vec4;
    %pushi/vec4 16, 0, 64;
    %cmp/u;
    %jmp/1 T_8.4, 6;
    %dup/vec4;
    %pushi/vec4 20, 0, 64;
    %cmp/u;
    %jmp/1 T_8.5, 6;
    %dup/vec4;
    %pushi/vec4 24, 0, 64;
    %cmp/u;
    %jmp/1 T_8.6, 6;
    %dup/vec4;
    %pushi/vec4 28, 0, 64;
    %cmp/u;
    %jmp/1 T_8.7, 6;
    %dup/vec4;
    %pushi/vec4 32, 0, 64;
    %cmp/u;
    %jmp/1 T_8.8, 6;
    %pushi/vec4 4294967295, 4294967295, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.0 ;
    %pushi/vec4 3538044553, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.1 ;
    %pushi/vec4 3536506634, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.2 ;
    %pushi/vec4 2332688681, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.3 ;
    %pushi/vec4 3534968714, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.4 ;
    %pushi/vec4 2332688681, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.5 ;
    %pushi/vec4 3533430282, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.6 ;
    %pushi/vec4 2332688681, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.7 ;
    %pushi/vec4 4160914409, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.8 ;
    %pushi/vec4 4165108714, 0, 32;
    %store/vec4 v0x1acdcc0_0, 0, 32;
    %jmp T_8.10;
T_8.10 ;
    %pop/vec4 1;
    %jmp T_8;
    .thread T_8, $push;
    .scope S_0x1acc050;
T_9 ;
    %wait E_0x1acc230;
    %load/vec4 v0x1acc7a0_0;
    %dup/vec4;
    %pushi/vec4 1104, 0, 11;
    %cmp/x;
    %jmp/1 T_9.0, 4;
    %dup/vec4;
    %pushi/vec4 1360, 0, 11;
    %cmp/x;
    %jmp/1 T_9.1, 4;
    %dup/vec4;
    %pushi/vec4 1112, 0, 11;
    %cmp/x;
    %jmp/1 T_9.2, 4;
    %dup/vec4;
    %pushi/vec4 1624, 0, 11;
    %cmp/x;
    %jmp/1 T_9.3, 4;
    %dup/vec4;
    %pushi/vec4 1161, 1, 11;
    %cmp/x;
    %jmp/1 T_9.4, 4;
    %dup/vec4;
    %pushi/vec4 1673, 1, 11;
    %cmp/x;
    %jmp/1 T_9.5, 4;
    %dup/vec4;
    %pushi/vec4 1687, 3, 11;
    %cmp/x;
    %jmp/1 T_9.6, 4;
    %dup/vec4;
    %pushi/vec4 191, 31, 11;
    %cmp/x;
    %jmp/1 T_9.7, 4;
    %dup/vec4;
    %pushi/vec4 1447, 7, 11;
    %cmp/x;
    %jmp/1 T_9.8, 4;
    %dup/vec4;
    %pushi/vec4 1986, 0, 11;
    %cmp/x;
    %jmp/1 T_9.9, 4;
    %dup/vec4;
    %pushi/vec4 1984, 0, 11;
    %cmp/x;
    %jmp/1 T_9.10, 4;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 15, 15, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 3, 3, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.1 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 1, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.2 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 2, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.3 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 6, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.4 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 2, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.5 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 6, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.6 ;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 8, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 7, 3, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.7 ;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 15, 15, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 2, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.8 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 7, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 3, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.9 ;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 2, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.10 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc880_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc3b0_0, 0;
    %pushi/vec4 1, 1, 1;
    %assign/vec4 v0x1acc510_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc5d0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x1acc6e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acc470_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1accac0_0, 0;
    %pushi/vec4 2, 0, 4;
    %assign/vec4 v0x1acc2b0_0, 0;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v0x1acca00_0, 0;
    %jmp T_9.12;
T_9.12 ;
    %pop/vec4 1;
    %jmp T_9;
    .thread T_9, $push;
    .scope S_0x1ac9a20;
T_10 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x1acb0b0_0, 0, 32;
T_10.0 ;
    %load/vec4 v0x1acb0b0_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_10.1, 5;
    %pushi/vec4 0, 0, 64;
    %ix/getv/s 4, v0x1acb0b0_0;
    %store/vec4a v0x1acb190, 4, 0;
    %load/vec4 v0x1acb0b0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x1acb0b0_0, 0, 32;
    %jmp T_10.0;
T_10.1 ;
    %end;
    .thread T_10;
    .scope S_0x1ac9a20;
T_11 ;
    %wait E_0x1ac4650;
    %vpi_call 10 22 "$display", "regWr: %b, RW: %b, BusW: %h, reg2: %h, reg4: %h, reg9: %h", v0x1aca230_0, v0x1aca170_0, v0x1ac9e20_0, &A<v0x1acb190, 2>, &A<v0x1acb190, 4>, &A<v0x1acb190, 9> {0 0 0};
    %jmp T_11;
    .thread T_11;
    .scope S_0x1ac9a20;
T_12 ;
    %wait E_0x1ac9180;
    %load/vec4 v0x1aca230_0;
    %load/vec4 v0x1aca170_0;
    %pad/u 32;
    %pushi/vec4 31, 0, 32;
    %cmp/ne;
    %flag_get/vec4 4;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_12.0, 8;
    %delay 1000, 0;
    %load/vec4 v0x1ac9e20_0;
    %load/vec4 v0x1aca170_0;
    %pad/u 7;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1acb190, 0, 4;
T_12.0 ;
    %jmp T_12;
    .thread T_12;
    .scope S_0x1acb350;
T_13 ;
    %wait E_0x1acb4e0;
    %load/vec4 v0x1acb720_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 3;
    %cmp/u;
    %jmp/1 T_13.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 3;
    %cmp/u;
    %jmp/1 T_13.1, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 3;
    %cmp/u;
    %jmp/1 T_13.2, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 3;
    %cmp/u;
    %jmp/1 T_13.3, 6;
    %dup/vec4;
    %pushi/vec4 7, 3, 3;
    %cmp/u;
    %jmp/1 T_13.4, 6;
    %pushi/vec4 0, 0, 64;
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.6;
T_13.0 ;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 1, 21, 6;
    %replicate 53;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 12, 10, 5;
    %concat/vec4; draw_concat_vec4
    %pad/u 64;
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.6;
T_13.1 ;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 1, 20, 6;
    %replicate 56;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 8, 12, 5;
    %concat/vec4; draw_concat_vec4
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.6;
T_13.2 ;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 1, 25, 6;
    %replicate 39;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 25, 0, 2;
    %concat/vec4; draw_concat_vec4
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.6;
T_13.3 ;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 1, 23, 6;
    %replicate 45;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 19, 5, 4;
    %concat/vec4; draw_concat_vec4
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.6;
T_13.4 ;
    %load/vec4 v0x1acb8d0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_13.7, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_13.8, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_13.9, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 2;
    %cmp/u;
    %jmp/1 T_13.10, 6;
    %jmp T_13.11;
T_13.7 ;
    %pushi/vec4 0, 0, 48;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 16, 5, 4;
    %concat/vec4; draw_concat_vec4
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.11;
T_13.8 ;
    %pushi/vec4 0, 0, 32;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 16, 5, 4;
    %concat/vec4; draw_concat_vec4
    %concati/vec4 0, 0, 16;
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.11;
T_13.9 ;
    %pushi/vec4 0, 0, 16;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 16, 5, 4;
    %concat/vec4; draw_concat_vec4
    %concati/vec4 0, 0, 32;
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.11;
T_13.10 ;
    %load/vec4 v0x1acb7f0_0;
    %parti/s 16, 5, 4;
    %concati/vec4 0, 0, 48;
    %store/vec4 v0x1acb560_0, 0, 64;
    %jmp T_13.11;
T_13.11 ;
    %pop/vec4 1;
    %jmp T_13.6;
T_13.6 ;
    %pop/vec4 1;
    %jmp T_13;
    .thread T_13, $push;
    .scope S_0x1ac3cc0;
T_14 ;
    %wait E_0x1a3a250;
    %load/vec4 v0x1ac3f10_0;
    %cmpi/e 0, 0, 1;
    %jmp/0xz  T_14.0, 4;
    %load/vec4 v0x1ac3ff0_0;
    %assign/vec4 v0x1ac41c0_0, 0;
    %jmp T_14.1;
T_14.0 ;
    %load/vec4 v0x1ac3f10_0;
    %cmpi/e 1, 0, 1;
    %jmp/0xz  T_14.2, 4;
    %load/vec4 v0x1ac40d0_0;
    %assign/vec4 v0x1ac41c0_0, 0;
T_14.2 ;
T_14.1 ;
    %jmp T_14;
    .thread T_14, $push;
    .scope S_0x1ac32a0;
T_15 ;
    %wait E_0x1ac3530;
    %load/vec4 v0x1ac36b0_0;
    %cmpi/e 0, 0, 2;
    %jmp/0xz  T_15.0, 4;
    %load/vec4 v0x1ac3830_0;
    %assign/vec4 v0x1ac3af0_0, 0;
    %jmp T_15.1;
T_15.0 ;
    %load/vec4 v0x1ac36b0_0;
    %cmpi/e 1, 0, 2;
    %jmp/0xz  T_15.2, 4;
    %load/vec4 v0x1ac3910_0;
    %assign/vec4 v0x1ac3af0_0, 0;
    %jmp T_15.3;
T_15.2 ;
    %load/vec4 v0x1ac36b0_0;
    %cmpi/e 2, 0, 2;
    %jmp/0xz  T_15.4, 4;
    %load/vec4 v0x1ac3a20_0;
    %assign/vec4 v0x1ac3af0_0, 0;
T_15.4 ;
T_15.3 ;
T_15.1 ;
    %jmp T_15;
    .thread T_15, $push;
    .scope S_0x1ac2940;
T_16 ;
    %wait E_0x1aacba0;
    %load/vec4 v0x1ac2c90_0;
    %cmpi/e 0, 0, 2;
    %jmp/0xz  T_16.0, 4;
    %load/vec4 v0x1ac2df0_0;
    %assign/vec4 v0x1ac30e0_0, 0;
    %jmp T_16.1;
T_16.0 ;
    %load/vec4 v0x1ac2c90_0;
    %cmpi/e 1, 0, 2;
    %jmp/0xz  T_16.2, 4;
    %load/vec4 v0x1ac2ed0_0;
    %assign/vec4 v0x1ac30e0_0, 0;
    %jmp T_16.3;
T_16.2 ;
    %load/vec4 v0x1ac2c90_0;
    %cmpi/e 2, 0, 2;
    %jmp/0xz  T_16.4, 4;
    %load/vec4 v0x1ac3000_0;
    %assign/vec4 v0x1ac30e0_0, 0;
T_16.4 ;
T_16.3 ;
T_16.1 ;
    %jmp T_16;
    .thread T_16, $push;
    .scope S_0x1ac1c30;
T_17 ;
    %wait E_0x1a39d60;
    %load/vec4 v0x1ac1ef0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 4;
    %cmp/u;
    %jmp/1 T_17.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 4;
    %cmp/u;
    %jmp/1 T_17.1, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 4;
    %cmp/u;
    %jmp/1 T_17.2, 6;
    %dup/vec4;
    %pushi/vec4 6, 0, 4;
    %cmp/u;
    %jmp/1 T_17.3, 6;
    %dup/vec4;
    %pushi/vec4 7, 0, 4;
    %cmp/u;
    %jmp/1 T_17.4, 6;
    %dup/vec4;
    %pushi/vec4 8, 0, 4;
    %cmp/u;
    %jmp/1 T_17.5, 6;
    %jmp T_17.6;
T_17.0 ;
    %load/vec4 v0x1ac1ff0_0;
    %load/vec4 v0x1ac20d0_0;
    %and;
    %assign/vec4 v0x1ac2190_0, 0;
    %jmp T_17.6;
T_17.1 ;
    %load/vec4 v0x1ac1ff0_0;
    %load/vec4 v0x1ac20d0_0;
    %or;
    %assign/vec4 v0x1ac2190_0, 0;
    %jmp T_17.6;
T_17.2 ;
    %load/vec4 v0x1ac1ff0_0;
    %load/vec4 v0x1ac20d0_0;
    %add;
    %assign/vec4 v0x1ac2190_0, 0;
    %jmp T_17.6;
T_17.3 ;
    %load/vec4 v0x1ac1ff0_0;
    %load/vec4 v0x1ac20d0_0;
    %sub;
    %assign/vec4 v0x1ac2190_0, 0;
    %jmp T_17.6;
T_17.4 ;
    %load/vec4 v0x1ac20d0_0;
    %concati/vec4 0, 0, 16;
    %pad/u 64;
    %assign/vec4 v0x1ac2190_0, 0;
    %jmp T_17.6;
T_17.5 ;
    %load/vec4 v0x1ac20d0_0;
    %assign/vec4 v0x1ac2190_0, 0;
    %jmp T_17.6;
T_17.6 ;
    %pop/vec4 1;
    %jmp T_17;
    .thread T_17, $push;
    .scope S_0x1ac8920;
T_18 ;
    %wait E_0x1ac8ae0;
    %load/vec4 v0x1ac8b60_0;
    %cmpi/e 0, 0, 1;
    %jmp/0xz  T_18.0, 4;
    %load/vec4 v0x1ac8c40_0;
    %assign/vec4 v0x1ac8e10_0, 0;
    %jmp T_18.1;
T_18.0 ;
    %load/vec4 v0x1ac8b60_0;
    %cmpi/e 1, 0, 1;
    %jmp/0xz  T_18.2, 4;
    %load/vec4 v0x1ac8d20_0;
    %assign/vec4 v0x1ac8e10_0, 0;
T_18.2 ;
T_18.1 ;
    %jmp T_18;
    .thread T_18, $push;
    .scope S_0x1ac4340;
T_19 ;
    %pushi/vec4 0, 0, 64;
    %store/vec4 v0x1ac4930_0, 0, 64;
    %pushi/vec4 1, 0, 64;
    %store/vec4 v0x1ac4a30_0, 0, 64;
    %fork TD_ProcTest_v.uut.DataMemory.initset, S_0x1ac4730;
    %join;
    %pushi/vec4 8, 0, 64;
    %store/vec4 v0x1ac4930_0, 0, 64;
    %pushi/vec4 6, 0, 64;
    %store/vec4 v0x1ac4a30_0, 0, 64;
    %fork TD_ProcTest_v.uut.DataMemory.initset, S_0x1ac4730;
    %join;
    %pushi/vec4 16, 0, 64;
    %store/vec4 v0x1ac4930_0, 0, 64;
    %pushi/vec4 5, 0, 64;
    %store/vec4 v0x1ac4a30_0, 0, 64;
    %fork TD_ProcTest_v.uut.DataMemory.initset, S_0x1ac4730;
    %join;
    %pushi/vec4 24, 0, 64;
    %store/vec4 v0x1ac4930_0, 0, 64;
    %pushi/vec4 4290684894, 0, 36;
    %concati/vec4 182185727, 0, 28;
    %store/vec4 v0x1ac4a30_0, 0, 64;
    %fork TD_ProcTest_v.uut.DataMemory.initset, S_0x1ac4730;
    %join;
    %pushi/vec4 32, 0, 64;
    %store/vec4 v0x1ac4930_0, 0, 64;
    %pushi/vec4 0, 0, 64;
    %store/vec4 v0x1ac4a30_0, 0, 64;
    %fork TD_ProcTest_v.uut.DataMemory.initset, S_0x1ac4730;
    %join;
    %end;
    .thread T_19;
    .scope S_0x1ac4340;
T_20 ;
    %wait E_0x1ac46d0;
    %load/vec4 v0x1ac4d00_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_20.0, 8;
    %ix/getv 4, v0x1ac4b10_0;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 56, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 1, 0, 65;
    %ix/vec4 4;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 48, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 2, 0, 65;
    %ix/vec4 4;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 40, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 3, 0, 65;
    %ix/vec4 4;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 32, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 4, 0, 65;
    %ix/vec4 4;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 24, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 5, 0, 65;
    %ix/vec4 4;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 16, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 6, 0, 65;
    %ix/vec4 4;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 8, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 7, 0, 65;
    %ix/vec4 4;
    %load/vec4a v0x1ac5050, 4;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1ac4e40_0, 4, 5;
T_20.0 ;
    %jmp T_20;
    .thread T_20;
    .scope S_0x1ac4340;
T_21 ;
    %wait E_0x1ac4650;
    %load/vec4 v0x1ac4da0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_21.0, 8;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 56, 7;
    %ix/getv 3, v0x1ac4b10_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 48, 7;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 1, 0, 65;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 40, 7;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 2, 0, 65;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 32, 7;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 3, 0, 65;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 24, 6;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 4, 0, 65;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 16, 6;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 5, 0, 65;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 8, 5;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 6, 0, 65;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
    %load/vec4 v0x1ac4f70_0;
    %parti/s 8, 0, 2;
    %load/vec4 v0x1ac4b10_0;
    %pad/u 65;
    %addi 7, 0, 65;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x1ac5050, 0, 4;
T_21.0 ;
    %jmp T_21;
    .thread T_21;
    .scope S_0x1acba80;
T_22 ;
    %wait E_0x1ac4650;
    %load/vec4 v0x1acbe00_0;
    %load/vec4 v0x1acbed0_0;
    %ix/load 4, 2, 0;
    %flag_set/imm 4, 0;
    %shiftl 4;
    %add;
    %pad/u 1;
    %assign/vec4 v0x1acbc60_0, 0;
    %jmp T_22;
    .thread T_22;
    .scope S_0x1ac8fa0;
T_23 ;
    %wait E_0x1ac9270;
    %load/vec4 v0x1ac9840_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_23.0, 8;
    %load/vec4 v0x1ac93f0_0;
    %load/vec4 v0x1ac9310_0;
    %and;
    %flag_set/vec4 8;
    %load/vec4 v0x1ac9780_0;
    %flag_set/vec4 9;
    %flag_or 9, 8;
    %jmp/0xz  T_23.2, 9;
    %load/vec4 v0x1ac9650_0;
    %store/vec4 v0x1ac9570_0, 0, 64;
    %jmp T_23.3;
T_23.2 ;
    %load/vec4 v0x1ac94b0_0;
    %addi 4, 0, 64;
    %store/vec4 v0x1ac9570_0, 0, 64;
T_23.3 ;
    %jmp T_23.1;
T_23.0 ;
    %load/vec4 v0x1ac94b0_0;
    %store/vec4 v0x1ac9570_0, 0, 64;
T_23.1 ;
    %jmp T_23;
    .thread T_23, $push;
    .scope S_0x1ac19f0;
T_24 ;
    %wait E_0x1ac9180;
    %load/vec4 v0x1ad1170_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_24.0, 8;
    %load/vec4 v0x1ad0bc0_0;
    %assign/vec4 v0x1ad0570_0, 0;
    %load/vec4 v0x1ad07e0_0;
    %assign/vec4 v0x1ad08b0_0, 0;
    %jmp T_24.1;
T_24.0 ;
    %load/vec4 v0x1ad1490_0;
    %assign/vec4 v0x1ad0570_0, 0;
T_24.1 ;
    %jmp T_24;
    .thread T_24;
    .scope S_0x1ac19f0;
T_25 ;
    %wait E_0x1ac4650;
    %load/vec4 v0x1ad1170_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_25.0, 8;
    %load/vec4 v0x1acf6a0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_25.2, 8;
    %load/vec4 v0x1ad0570_0;
    %assign/vec4 v0x1acf5b0_0, 0;
    %load/vec4 v0x1ad07e0_0;
    %assign/vec4 v0x1acf770_0, 0;
    %load/vec4 v0x1ad07e0_0;
    %assign/vec4 v0x1acf810_0, 0;
T_25.2 ;
    %load/vec4 v0x1ace3b0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_25.4, 4;
    %load/vec4 v0x1ad10a0_0;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acf110_0, 4, 5;
    %load/vec4 v0x1ad0950_0;
    %ix/load 4, 1, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acf110_0, 4, 5;
    %load/vec4 v0x1ad03d0_0;
    %assign/vec4 v0x1acec20_0, 0;
    %load/vec4 v0x1acf770_0;
    %parti/s 5, 0, 2;
    %assign/vec4 v0x1acf1f0_0, 0;
    %load/vec4 v0x1ad0a20_0;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acee70_0, 4, 5;
    %load/vec4 v0x1ad0af0_0;
    %ix/load 4, 1, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acee70_0, 4, 5;
    %load/vec4 v0x1ad04a0_0;
    %ix/load 4, 2, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acee70_0, 4, 5;
    %load/vec4 v0x1ad1530_0;
    %ix/load 4, 3, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acee70_0, 4, 5;
    %load/vec4 v0x1ad0240_0;
    %assign/vec4 v0x1acedd0_0, 0;
    %jmp T_25.5;
T_25.4 ;
    %pushi/vec4 0, 0, 1;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acf110_0, 4, 5;
    %pushi/vec4 0, 0, 1;
    %ix/load 4, 1, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acf110_0, 4, 5;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x1acec20_0, 0;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v0x1acf1f0_0, 0;
    %pushi/vec4 0, 0, 1;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acee70_0, 4, 5;
    %pushi/vec4 0, 0, 1;
    %ix/load 4, 1, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acee70_0, 4, 5;
    %pushi/vec4 0, 0, 1;
    %ix/load 4, 2, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x1acee70_0, 4, 5;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v0x1acedd0_0, 0;
T_25.5 ;
    %load/vec4 v0x1acf5b0_0;
    %assign/vec4 v0x1acef30_0, 0;
    %load/vec4 v0x1ad0f00_0;
    %assign/vec4 v0x1acf2b0_0, 0;
    %load/vec4 v0x1ad0fd0_0;
    %assign/vec4 v0x1acf380_0, 0;
    %load/vec4 v0x1ad0710_0;
    %assign/vec4 v0x1acf020_0, 0;
    %load/vec4 v0x1ad07e0_0;
    %parti/s 11, 21, 6;
    %assign/vec4 v0x1aceb40_0, 0;
    %load/vec4 v0x1ad1210_0;
    %assign/vec4 v0x1acf450_0, 0;
    %load/vec4 v0x1ad12b0_0;
    %assign/vec4 v0x1acf4f0_0, 0;
    %load/vec4 v0x1acf110_0;
    %assign/vec4 v0x1ace670_0, 0;
    %load/vec4 v0x1acee70_0;
    %assign/vec4 v0x1ace4f0_0, 0;
    %load/vec4 v0x1ad0bc0_0;
    %assign/vec4 v0x1ace5b0_0, 0;
    %load/vec4 v0x1ad19e0_0;
    %assign/vec4 v0x1ace7f0_0, 0;
    %load/vec4 v0x1ad0300_0;
    %assign/vec4 v0x1ace450_0, 0;
    %load/vec4 v0x1acf380_0;
    %assign/vec4 v0x1ace8c0_0, 0;
    %load/vec4 v0x1acf1f0_0;
    %assign/vec4 v0x1ace730_0, 0;
    %load/vec4 v0x1ace110_0;
    %pad/u 64;
    %assign/vec4 v0x1ace5b0_0, 0;
    %load/vec4 v0x1ace670_0;
    %assign/vec4 v0x1acf9e0_0, 0;
    %load/vec4 v0x1ad0640_0;
    %assign/vec4 v0x1acfd70_0, 0;
    %load/vec4 v0x1ace450_0;
    %assign/vec4 v0x1acf8f0_0, 0;
    %load/vec4 v0x1ace730_0;
    %assign/vec4 v0x1acfcb0_0, 0;
T_25.0 ;
    %jmp T_25;
    .thread T_25;
    .scope S_0x19f53e0;
T_26 ;
    %vpi_call 2 11 "$dumpfile", "singlecycle.vcd" {0 0 0};
    %vpi_call 2 12 "$dumpvars" {0 0 0};
    %end;
    .thread T_26;
    .scope S_0x19f53e0;
T_27 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x1ad1c20_0, 0, 1;
    %pushi/vec4 0, 0, 64;
    %store/vec4 v0x1ad20f0_0, 0, 64;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v0x1ad2030_0, 0, 8;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v0x1ad21e0_0, 0, 16;
    %delay 120000, 0;
    %delay 1000, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x1ad1c20_0, 0, 1;
    %pushi/vec4 0, 0, 64;
    %store/vec4 v0x1ad20f0_0, 0, 64;
    %delay 120000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x1ad1c20_0, 0, 1;
T_27.0 ;
    %load/vec4 v0x1ad1db0_0;
    %cmpi/u 52, 0, 64;
    %jmp/0xz T_27.1, 5;
    %delay 120000, 0;
    %jmp T_27.0;
T_27.1 ;
    %delay 120000, 0;
    %vpi_call 2 100 "$finish" {0 0 0};
    %end;
    .thread T_27;
    .scope S_0x19f53e0;
T_28 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x1ad1b60_0, 0, 1;
    %end;
    .thread T_28;
    .scope S_0x19f53e0;
T_29 ;
    %delay 60000, 0;
    %load/vec4 v0x1ad1b60_0;
    %inv;
    %store/vec4 v0x1ad1b60_0, 0, 1;
    %delay 60000, 0;
    %load/vec4 v0x1ad1b60_0;
    %inv;
    %store/vec4 v0x1ad1b60_0, 0, 1;
    %load/vec4 v0x1ad21e0_0;
    %addi 1, 0, 16;
    %store/vec4 v0x1ad21e0_0, 0, 16;
    %jmp T_29;
    .thread T_29;
    .scope S_0x19f53e0;
T_30 ;
    %wait E_0x1a3a0c0;
    %load/vec4 v0x1ad21e0_0;
    %cmpi/e 255, 0, 16;
    %jmp/0xz  T_30.0, 4;
    %vpi_call 2 118 "$display", "Watchdog Timer Expired." {0 0 0};
    %vpi_call 2 119 "$finish" {0 0 0};
T_30.0 ;
    %jmp T_30;
    .thread T_30, $push;
# The file index is used to find the file name in the following table.
:file_names 15;
    "N/A";
    "<interactive>";
    "Processor_tb.v";
    "Processor.v";
    "./ALU.v";
    "./3To1Mux.v";
    "./2To1Mux.v";
    "./DataMemory.v";
    "./ForwardingUnit.v";
    "./PC.v";
    "./RegisterFile.v";
    "./SignExtender.v";
    "./Controller.v";
    "./HazardDetectionUnit.v";
    "./InstructionMemory.v";