diff --git a/libclc/libspirv/lib/amdgcn-amdhsa/SOURCES b/libclc/libspirv/lib/amdgcn-amdhsa/SOURCES deleted file mode 100644 index eaddcde7d2368..0000000000000 --- a/libclc/libspirv/lib/amdgcn-amdhsa/SOURCES +++ /dev/null @@ -1,65 +0,0 @@ -atomic/atomic_and.cl -atomic/atomic_max.cl -atomic/atomic_min.cl -atomic/atomic_or.cl -atomic/atomic_xor.cl -group/group_ballot.cl -group/collectives.cl -group/collectives_helpers.ll -conversion/GenericCastToPtrExplicit.cl -synchronization/barrier.cl -images/image_common.cl -images/image.cl -images/image_array.cl -math/acos.cl -math/acosh.cl -math/asin.cl -math/asinh.cl -math/atan.cl -math/atan2.cl -math/atanh.cl -math/cbrt.cl -math/copysign.cl -math/cos.cl -math/cosh.cl -math/cospi.cl -math/erf.cl -math/erfc.cl -math/exp10.cl -math/exp2.cl -math/expm1.cl -math/fdim.cl -math/fmod.cl -math/frexp.cl -math/hypot.cl -math/ilogb.cl -math/ldexp.cl -math/log2.cl -math/log10.cl -math/log1p.cl -math/logb.cl -math/modf.cl -math/nextafter.cl -math/pow.cl -math/remainder.cl -math/round.cl -math/rsqrt.cl -math/sin.cl -math/sincos.cl -math/sinh.cl -math/tan.cl -math/tanh.cl -workitem/get_global_size.cl -workitem/get_group_id.cl -workitem/get_local_id.cl -workitem/get_local_linear_id.cl -workitem/get_local_size.cl -workitem/get_num_groups.cl -workitem/get_num_sub_groups.cl -workitem/get_max_sub_group_size.cl -workitem/get_sub_group_id.cl -workitem/get_sub_group_local_id.cl -workitem/get_work_dim.cl -misc/sub_group_shuffle.cl -async/wait_group_events.cl -assert/__assert_fail.cl diff --git a/libclc/libspirv/lib/ptx-nvidiacl/images/1.s b/libclc/libspirv/lib/ptx-nvidiacl/images/1.s deleted file mode 100644 index d1ff22c48db6d..0000000000000 --- a/libclc/libspirv/lib/ptx-nvidiacl/images/1.s +++ /dev/null @@ -1,2318 +0,0 @@ -// -// Generated by LLVM NVPTX Back-End -// - -.version 6.3 -.target sm_75 -.address_size 32 - - // .globl __clc__sampled_image_unpack_image // -- Begin function __clc__sampled_image_unpack_image - // @__clc__sampled_image_unpack_image -.visible .func (.param .b64 func_retval0) __clc__sampled_image_unpack_image( - .param .b64 __clc__sampled_image_unpack_image_param_0, - .param .b32 __clc__sampled_image_unpack_image_param_1 -) -{ - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc__sampled_image_unpack_image_param_0]; - st.param.b64 [func_retval0], %rd1; - ret; - // -- End function -} - // .globl __clc__sampled_image_unpack_sampler // -- Begin function __clc__sampled_image_unpack_sampler -.visible .func (.param .b32 func_retval0) __clc__sampled_image_unpack_sampler( - .param .b64 __clc__sampled_image_unpack_sampler_param_0, - .param .b32 __clc__sampled_image_unpack_sampler_param_1 -) // @__clc__sampled_image_unpack_sampler -{ - .reg .b32 %r<2>; - -// %bb.0: - ld.param.b32 %r1, [__clc__sampled_image_unpack_sampler_param_1]; - st.param.b32 [func_retval0], %r1; - ret; - // -- End function -} - // .globl __clc__sampled_image_pack // -- Begin function __clc__sampled_image_pack -.visible .func (.param .align 8 .b8 func_retval0[16]) __clc__sampled_image_pack( - .param .b64 __clc__sampled_image_pack_param_0, - .param .b32 __clc__sampled_image_pack_param_1 -) // @__clc__sampled_image_pack -{ - .reg .b32 %r<2>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc__sampled_image_pack_param_0]; - ld.param.b32 %r1, [__clc__sampled_image_pack_param_1]; - st.param.b32 [func_retval0+8], %r1; - st.param.b64 [func_retval0], %rd1; - ret; - // -- End function -} - // .globl __clc__sampler_extract_normalized_coords_prop // -- Begin function __clc__sampler_extract_normalized_coords_prop -.visible .func (.param .b32 func_retval0) __clc__sampler_extract_normalized_coords_prop( - .param .b32 __clc__sampler_extract_normalized_coords_prop_param_0 -) // @__clc__sampler_extract_normalized_coords_prop -{ - .reg .b32 %r<3>; - -// %bb.0: - ld.param.b32 %r1, [__clc__sampler_extract_normalized_coords_prop_param_0]; - and.b32 %r2, %r1, 1; - st.param.b32 [func_retval0], %r2; - ret; - // -- End function -} - // .globl __clc__sampler_extract_filter_mode_prop // -- Begin function __clc__sampler_extract_filter_mode_prop -.visible .func (.param .b32 func_retval0) __clc__sampler_extract_filter_mode_prop( - .param .b32 __clc__sampler_extract_filter_mode_prop_param_0 -) // @__clc__sampler_extract_filter_mode_prop -{ - .reg .b32 %r<3>; - -// %bb.0: - ld.param.b32 %r1, [__clc__sampler_extract_filter_mode_prop_param_0]; - bfe.u32 %r2, %r1, 1, 1; - st.param.b32 [func_retval0], %r2; - ret; - // -- End function -} - // .globl __clc__sampler_extract_addressing_mode_prop // -- Begin function __clc__sampler_extract_addressing_mode_prop -.visible .func (.param .b32 func_retval0) __clc__sampler_extract_addressing_mode_prop( - .param .b32 __clc__sampler_extract_addressing_mode_prop_param_0 -) // @__clc__sampler_extract_addressing_mode_prop -{ - .reg .b32 %r<3>; - -// %bb.0: - ld.param.b32 %r1, [__clc__sampler_extract_addressing_mode_prop_param_0]; - shr.u32 %r2, %r1, 2; - st.param.b32 [func_retval0], %r2; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i16_trap // -- Begin function __clc_llvm_nvvm_suld_1d_v4i16_trap -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i16_trap( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i16_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i16_trap_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i16_trap -{ - .reg .b16 %rs<5>; - .reg .b32 %r<2>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i16_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i16_trap_param_1]; - // begin inline asm - suld.b.1d.v4.b16.trap {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i16_trap // -- Begin function __clc_llvm_nvvm_suld_2d_v4i16_trap -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i16_trap( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i16_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_trap_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i16_trap -{ - .reg .b16 %rs<5>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i16_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i16_trap_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i16_trap_param_2]; - // begin inline asm - suld.b.2d.v4.b16.trap {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i16_trap // -- Begin function __clc_llvm_nvvm_suld_3d_v4i16_trap -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i16_trap( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i16_trap -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_3]; - // begin inline asm - suld.b.3d.v4.b16.trap {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i16_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<2>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i16_clamp_param_1]; - // begin inline asm - suld.b.1d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i16_clamp_param_2]; - // begin inline asm - suld.b.2d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_3]; - // begin inline asm - suld.b.3d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i16_zero // -- Begin function __clc_llvm_nvvm_suld_1d_v4i16_zero -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i16_zero( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i16_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i16_zero_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i16_zero -{ - .reg .b16 %rs<5>; - .reg .b32 %r<2>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i16_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i16_zero_param_1]; - // begin inline asm - suld.b.1d.v4.b16.zero {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i16_zero // -- Begin function __clc_llvm_nvvm_suld_2d_v4i16_zero -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i16_zero( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i16_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_zero_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i16_zero -{ - .reg .b16 %rs<5>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i16_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i16_zero_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i16_zero_param_2]; - // begin inline asm - suld.b.2d.v4.b16.zero {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i16_zero // -- Begin function __clc_llvm_nvvm_suld_3d_v4i16_zero -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i16_zero( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i16_zero -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_3]; - // begin inline asm - suld.b.3d.v4.b16.zero {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i32_trap // -- Begin function __clc_llvm_nvvm_suld_1d_v4i32_trap -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_v4i32_trap( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i32_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i32_trap_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i32_trap -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i32_trap_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_1d_v4i32_trap_param_1]; - // begin inline asm - suld.b.1d.v4.b32.trap {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i32_trap // -- Begin function __clc_llvm_nvvm_suld_2d_v4i32_trap -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_v4i32_trap( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i32_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_trap_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i32_trap -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i32_trap_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_2d_v4i32_trap_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_2d_v4i32_trap_param_2]; - // begin inline asm - suld.b.2d.v4.b32.trap {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i32_trap // -- Begin function __clc_llvm_nvvm_suld_3d_v4i32_trap -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_3d_v4i32_trap( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i32_trap -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_3]; - // begin inline asm - suld.b.3d.v4.b32.trap {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i32_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i32_clamp -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i32_clamp_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_1d_v4i32_clamp_param_1]; - // begin inline asm - suld.b.1d.v4.b32.clamp {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i32_clamp -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i32_clamp_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_2d_v4i32_clamp_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_2d_v4i32_clamp_param_2]; - // begin inline asm - suld.b.2d.v4.b32.clamp {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_3d_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i32_clamp -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_3]; - // begin inline asm - suld.b.3d.v4.b32.clamp {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i32_zero // -- Begin function __clc_llvm_nvvm_suld_1d_v4i32_zero -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_v4i32_zero( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i32_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i32_zero_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i32_zero -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i32_zero_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_1d_v4i32_zero_param_1]; - // begin inline asm - suld.b.1d.v4.b32.zero {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i32_zero // -- Begin function __clc_llvm_nvvm_suld_2d_v4i32_zero -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_v4i32_zero( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i32_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_zero_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i32_zero -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i32_zero_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_2d_v4i32_zero_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_2d_v4i32_zero_param_2]; - // begin inline asm - suld.b.2d.v4.b32.zero {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i32_zero // -- Begin function __clc_llvm_nvvm_suld_3d_v4i32_zero -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_3d_v4i32_zero( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i32_zero -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_3]; - // begin inline asm - suld.b.3d.v4.b32.zero {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_1d_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v2i8_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<2>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v2i8_clamp_param_1]; - // begin inline asm - suld.b.1d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1}]; - // end inline asm - st.param.v2.b16 [func_retval0], {%rs1, %rs2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_2d_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v2i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v2i8_clamp_param_2]; - // begin inline asm - suld.b.2d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v2.b16 [func_retval0], {%rs1, %rs2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_3d_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_3]; - // begin inline asm - suld.b.3d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v2.b16 [func_retval0], {%rs1, %rs2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i8_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<2>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i8_clamp_param_1]; - // begin inline asm - suld.b.1d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i8_clamp_param_2]; - // begin inline asm - suld.b.2d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_3]; - // begin inline asm - suld.b.3d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4i32_f32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4i32_f32 -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_v4i32_f32_param_1]; - // begin inline asm - tex.1d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_f32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4i32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_v4i32_f32_param_2]; - // begin inline asm - tex.2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4i32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_3]; - // begin inline asm - tex.3d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4j32_f32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4j32_f32 -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_v4j32_f32_param_1]; - // begin inline asm - tex.1d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_f32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4j32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_v4j32_f32_param_2]; - // begin inline asm - tex.2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4j32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_3]; - // begin inline asm - tex.3d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4f32_f32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4f32_f32 -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_v4f32_f32_param_1]; - // begin inline asm - tex.1d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4f32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_v4f32_f32_param_2]; - // begin inline asm - tex.2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4f32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_3]; - // begin inline asm - tex.3d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_r_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_r_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_r_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_r_2d_v4f32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_2]; - // begin inline asm - tld4.r.2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_g_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_g_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_g_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_g_2d_v4f32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_2]; - // begin inline asm - tld4.g.2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_b_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_b_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_b_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_b_2d_v4f32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_2]; - // begin inline asm - tld4.b.2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_a_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_a_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_a_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_a_2d_v4f32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_2]; - // begin inline asm - tld4.a.2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_r_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_r_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_r_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_r_2d_v4s32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_2]; - // begin inline asm - tld4.r.2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_g_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_g_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_g_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_g_2d_v4s32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_2]; - // begin inline asm - tld4.g.2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_b_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_b_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_b_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_b_2d_v4s32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_2]; - // begin inline asm - tld4.b.2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_a_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_a_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_a_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_a_2d_v4s32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_2]; - // begin inline asm - tld4.a.2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_r_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_r_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_r_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_r_2d_v4u32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_2]; - // begin inline asm - tld4.r.2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_g_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_g_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_g_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_g_2d_v4u32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_2]; - // begin inline asm - tld4.g.2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_b_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_b_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_b_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_b_2d_v4u32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_2]; - // begin inline asm - tld4.b.2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_a_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_a_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_a_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_a_2d_v4u32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_2]; - // begin inline asm - tld4.a.2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4i32_s32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4i32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4i32_s32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4i32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4i32_s32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4i32_s32 -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4i32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_v4i32_s32_param_1]; - // begin inline asm - tex.1d.v4.s32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4i32_s32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4i32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4i32_s32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4i32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_s32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4i32_s32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4i32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_v4i32_s32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_v4i32_s32_param_2]; - // begin inline asm - tex.2d.v4.s32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4i32_s32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4i32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4i32_s32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4i32_s32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_3]; - // begin inline asm - tex.3d.v4.s32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4j32_s32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4j32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4j32_s32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4j32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4j32_s32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4j32_s32 -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4j32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_v4j32_s32_param_1]; - // begin inline asm - tex.1d.v4.u32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4j32_s32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4j32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4j32_s32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4j32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_s32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4j32_s32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4j32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_v4j32_s32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_v4j32_s32_param_2]; - // begin inline asm - tex.2d.v4.s32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4j32_s32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4j32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4j32_s32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4j32_s32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_3]; - // begin inline asm - tex.3d.v4.u32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4f32_s32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4f32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4f32_s32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4f32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4f32_s32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4f32_s32 -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4f32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_v4f32_s32_param_1]; - // begin inline asm - tex.1d.v4.f32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4f32_s32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4f32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4f32_s32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4f32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_s32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4f32_s32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4f32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_v4f32_s32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_v4f32_s32_param_2]; - // begin inline asm - tex.2d.v4.f32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4f32_s32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4f32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4f32_s32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4f32_s32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_3]; - // begin inline asm - tex.3d.v4.f32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_level_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_level_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_level_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tex_1d_level_v4f32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_2]; - // begin inline asm - tex.level.1d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}], %r6; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_level_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_level_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_level_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_2d_level_v4f32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_3]; - // begin inline asm - tex.level.2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}], %r7; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_level_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_level_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_level_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_4 -) // @__clc_llvm_nvvm_tex_3d_level_v4f32_f32 -{ - .reg .b32 %r<9>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_4]; - // begin inline asm - tex.level.3d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}], %r8; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_level_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_level_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_level_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_2 -) // @__clc_llvm_nvvm_tex_1d_level_v4i32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_2]; - // begin inline asm - tex.level.1d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}], %r6; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_level_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_level_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_level_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_2d_level_v4i32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_3]; - // begin inline asm - tex.level.2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}], %r7; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_level_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_level_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_level_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_4 -) // @__clc_llvm_nvvm_tex_3d_level_v4i32_f32 -{ - .reg .b32 %r<9>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_4]; - // begin inline asm - tex.level.3d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}], %r8; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_level_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_level_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_level_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_2 -) // @__clc_llvm_nvvm_tex_1d_level_v4j32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_2]; - // begin inline asm - tex.level.1d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}], %r6; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_level_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_level_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_level_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_2d_level_v4j32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_3]; - // begin inline asm - tex.level.2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}], %r7; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_level_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_level_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_level_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_4 -) // @__clc_llvm_nvvm_tex_3d_level_v4j32_f32 -{ - .reg .b32 %r<9>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_4]; - // begin inline asm - tex.level.3d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}], %r8; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_grad_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_grad_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_grad_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_1d_grad_v4f32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_3]; - // begin inline asm - tex.grad.1d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}], {%r6}, {%r7}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_grad_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_grad_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_grad_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_6 -) // @__clc_llvm_nvvm_tex_2d_grad_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_4]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_5]; - ld.param.b32 %r10, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_6]; - // begin inline asm - tex.grad.2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}], {%r7, %r8}, {%r9, %r10}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_grad_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_grad_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_grad_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_6, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_7, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_8, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_9 -) // @__clc_llvm_nvvm_tex_3d_grad_v4f32_f32 -{ - .reg .b32 %r<14>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_4]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_5]; - ld.param.b32 %r10, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_6]; - ld.param.b32 %r11, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_7]; - ld.param.b32 %r12, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_8]; - ld.param.b32 %r13, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_9]; - // begin inline asm - tex.grad.3d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}], {%r8, %r9, %r10, %r10}, {%r11, %r12, %r13, %r13}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_grad_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_grad_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_grad_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_1d_grad_v4i32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_3]; - // begin inline asm - tex.grad.1d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}], {%r6}, {%r7}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_grad_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_grad_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_grad_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_6 -) // @__clc_llvm_nvvm_tex_2d_grad_v4i32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_4]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_5]; - ld.param.b32 %r10, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_6]; - // begin inline asm - tex.grad.2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}], {%r7, %r8}, {%r9, %r10}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_grad_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_grad_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_grad_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_6, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_7, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_8, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_9 -) // @__clc_llvm_nvvm_tex_3d_grad_v4i32_f32 -{ - .reg .b32 %r<14>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_4]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_5]; - ld.param.b32 %r10, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_6]; - ld.param.b32 %r11, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_7]; - ld.param.b32 %r12, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_8]; - ld.param.b32 %r13, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_9]; - // begin inline asm - tex.grad.3d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}], {%r8, %r9, %r10, %r10}, {%r11, %r12, %r13, %r13}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_grad_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_grad_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_grad_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_1d_grad_v4j32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_3]; - // begin inline asm - tex.grad.1d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5}], {%r6}, {%r7}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_grad_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_grad_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_grad_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_6 -) // @__clc_llvm_nvvm_tex_2d_grad_v4j32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_4]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_5]; - ld.param.b32 %r10, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_6]; - // begin inline asm - tex.grad.2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}], {%r7, %r8}, {%r9, %r10}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_grad_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_grad_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_grad_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_6, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_7, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_8, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_9 -) // @__clc_llvm_nvvm_tex_3d_grad_v4j32_f32 -{ - .reg .b32 %r<14>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_3]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_4]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_5]; - ld.param.b32 %r10, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_6]; - ld.param.b32 %r11, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_7]; - ld.param.b32 %r12, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_8]; - ld.param.b32 %r13, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_9]; - // begin inline asm - tex.grad.3d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}], {%r8, %r9, %r10, %r10}, {%r11, %r12, %r13, %r13}; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_cube_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_cube_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_cube_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_cube_v4f32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_3]; - // begin inline asm - tex.cube.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_cube_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_cube_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_cube_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_cube_v4i32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_3]; - // begin inline asm - tex.cube.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_cube_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_cube_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_cube_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_cube_v4j32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_3]; - // begin inline asm - tex.cube.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_1d_array_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_2]; - // begin inline asm - suld.b.a1d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v2.b16 [func_retval0], {%rs1, %rs2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_2d_array_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_3]; - // begin inline asm - suld.b.a2d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v2.b16 [func_retval0], {%rs1, %rs2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_array_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_2]; - // begin inline asm - suld.b.a1d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_array_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_3]; - // begin inline asm - suld.b.a2d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v2i16_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v2i16_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_1d_array_v2i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v2i16_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_2]; - // begin inline asm - suld.b.a1d.v2.b16.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v2.b16 [func_retval0], {%rs1, %rs2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v2i16_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v2i16_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_2d_array_v2i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v2i16_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_3]; - // begin inline asm - suld.b.a2d.v2.b16.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v2.b16 [func_retval0], {%rs1, %rs2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_array_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_2]; - // begin inline asm - suld.b.a1d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_array_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_3]; - // begin inline asm - suld.b.a2d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - // end inline asm - st.param.v4.b16 [func_retval0], {%rs1, %rs2, %rs3, %rs4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v2i32_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v2i32_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_array_v2i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v2i32_clamp -{ - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_0]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_1]; - ld.param.b32 %r4, [__clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_2]; - // begin inline asm - suld.b.a1d.v2.b32.clamp {%r1, %r2}, [%rd1, {%r3, %r4}]; - // end inline asm - st.param.v2.b32 [func_retval0], {%r1, %r2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v2i32_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v2i32_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_array_v2i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v2i32_clamp -{ - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_0]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_1]; - ld.param.b32 %r4, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_2]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_3]; - // begin inline asm - suld.b.a2d.v2.b32.clamp {%r1, %r2}, [%rd1, {%r3, %r4, %r5, %r5}]; - // end inline asm - st.param.v2.b32 [func_retval0], {%r1, %r2}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_array_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v4i32_clamp -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_2]; - // begin inline asm - suld.b.a1d.v4.b32.clamp {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_array_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v4i32_clamp -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_3]; - // begin inline asm - suld.b.a2d.v4.b32.clamp {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_2]; - // begin inline asm - tex.a1d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_3]; - // begin inline asm - tex.a2d.v4.f32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_2]; - // begin inline asm - tex.a1d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_3]; - // begin inline asm - tex.a2d.v4.s32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_2]; - // begin inline asm - tex.a1d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_3]; - // begin inline asm - tex.a2d.v4.u32.f32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_2]; - // begin inline asm - tex.a1d.v4.f32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_3]; - // begin inline asm - tex.a2d.v4.f32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_2]; - // begin inline asm - tex.a1d.v4.s32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_3]; - // begin inline asm - tex.a2d.v4.s32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32 -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_2]; - // begin inline asm - tex.a1d.v4.u32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32 -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_0]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_1]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_2]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_3]; - // begin inline asm - tex.a2d.v4.u32.s32 {%r1, %r2, %r3, %r4}, [%rd1, {%r5, %r6, %r7, %r7}]; - // end inline asm - st.param.v4.b32 [func_retval0], {%r1, %r2, %r3, %r4}; - ret; - // -- End function -} diff --git a/libclc/libspirv/lib/ptx-nvidiacl/images/image_helpers.cl.bak b/libclc/libspirv/lib/ptx-nvidiacl/images/image_helpers.cl.bak deleted file mode 100644 index 353408875975c..0000000000000 --- a/libclc/libspirv/lib/ptx-nvidiacl/images/image_helpers.cl.bak +++ /dev/null @@ -1,825 +0,0 @@ -// NVVM Image Helper Intrinsics - Inline PTX Assembly Implementation - -// Vector type definitions -typedef short __attribute__((ext_vector_type(2))) short2; -typedef short __attribute__((ext_vector_type(4))) short4; -typedef int __attribute__((ext_vector_type(2))) int2; -typedef int __attribute__((ext_vector_type(4))) int4; -typedef unsigned int __attribute__((ext_vector_type(2))) uint2; -typedef unsigned int __attribute__((ext_vector_type(4))) uint4; -typedef float __attribute__((ext_vector_type(4))) float4; -typedef unsigned int uint; -typedef unsigned long ulong; - -// Struct definitions matching NVVM intrinsic return types -typedef struct { - short x, y, z, w; -} __nvvm_v4i16_t; -typedef struct { - short x, y; -} __nvvm_v2i16_t; -typedef struct { - int x, y, z, w; -} __nvvm_v4i32_t; -typedef struct { - int x, y; -} __nvvm_v2i32_t; -typedef struct { - uint x, y, z, w; -} __nvvm_v4u32_t; -typedef struct { - uint x, y; -} __nvvm_v2u32_t; -typedef struct { - float x, y, z, w; -} __nvvm_v4f32_t; - -// Struct-to-vector conversion helpers -inline short4 __nvvm_v4i16_to_vec(__nvvm_v4i16_t s) { - union { - __nvvm_v4i16_t s; - short4 v; - } u; - u.s = s; - return u.v; -} - -inline short2 __nvvm_v2i16_to_vec(__nvvm_v2i16_t s) { - union { - __nvvm_v2i16_t s; - short2 v; - } u; - u.s = s; - return u.v; -} - -inline int4 __nvvm_v4i32_to_vec(__nvvm_v4i32_t s) { - union { - __nvvm_v4i32_t s; - int4 v; - } u; - u.s = s; - return u.v; -} - -inline int2 __nvvm_v2i32_to_vec(__nvvm_v2i32_t s) { - union { - __nvvm_v2i32_t s; - int2 v; - } u; - u.s = s; - return u.v; -} - -inline uint4 __nvvm_v4u32_to_vec(__nvvm_v4u32_t s) { - union { - __nvvm_v4u32_t s; - uint4 v; - } u; - u.s = s; - return u.v; -} - -inline uint2 __nvvm_v2u32_to_vec(__nvvm_v2u32_t s) { - union { - __nvvm_v2u32_t s; - uint2 v; - } u; - u.s = s; - return u.v; -} - -inline float4 __nvvm_v4f32_to_vec(__nvvm_v4f32_t s) { - union { - __nvvm_v4f32_t s; - float4 v; - } u; - u.s = s; - return u.v; -} - -// Sampled image pack/unpack helpers -ulong __clc__sampled_image_unpack_image(ulong img, uint sampl) { return img; } - -uint __clc__sampled_image_unpack_sampler(ulong img, uint sampl) { - return sampl; -} - -typedef struct { - ulong img; - uint sampl; -} __clc_sampled_image_t; - -__clc_sampled_image_t __clc__sampled_image_pack(ulong img, uint sampl) { - __clc_sampled_image_t result; - result.img = img; - result.sampl = sampl; - return result; -} - -// Sampler property extraction -uint __clc__sampler_extract_normalized_coords_prop(uint sampl) { - return sampl & 1; -} - -uint __clc__sampler_extract_filter_mode_prop(uint sampl) { - return (sampl >> 1) & 1; -} - -uint __clc__sampler_extract_addressing_mode_prop(uint sampl) { - return sampl >> 2; -} - -// NVVM Surface Load Intrinsics - v4i16 (trap/clamp/zero) -short4 __clc_llvm_nvvm_suld_1d_v4i16_trap(ulong img, int x) { - __nvvm_v4i16_t r; - __asm__("suld.b.1d.v4.b16.trap {%0, %1, %2, %3}, [%4, {%5}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_2d_v4i16_trap(ulong img, int x, int y) { - __nvvm_v4i16_t r; - __asm__("suld.b.2d.v4.b16.trap {%0, %1, %2, %3}, [%4, {%5, %6}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_3d_v4i16_trap(ulong img, int x, int y, int z) { - __nvvm_v4i16_t r; - __asm__( - "suld.b.3d.v4.b16.trap {%0, %1, %2, %3}, [%4, {%5, %6, %7, %7}];" - : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_1d_v4i16_clamp(ulong img, int x) { - __nvvm_v4i16_t r; - __asm__("suld.b.1d.v4.b16.clamp {%0, %1, %2, %3}, [%4, {%5}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_2d_v4i16_clamp(ulong img, int x, int y) { - __nvvm_v4i16_t r; - __asm__("suld.b.2d.v4.b16.clamp {%0, %1, %2, %3}, [%4, {%5, %6}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_3d_v4i16_clamp(ulong img, int x, int y, int z) { - __nvvm_v4i16_t r; - __asm__( - "suld.b.3d.v4.b16.clamp {%0, %1, %2, %3}, [%4, {%5, %6, %7, %7}];" - : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_1d_v4i16_zero(ulong img, int x) { - __nvvm_v4i16_t r; - __asm__("suld.b.1d.v4.b16.zero {%0, %1, %2, %3}, [%4, {%5}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_2d_v4i16_zero(ulong img, int x, int y) { - __nvvm_v4i16_t r; - __asm__("suld.b.2d.v4.b16.zero {%0, %1, %2, %3}, [%4, {%5, %6}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_3d_v4i16_zero(ulong img, int x, int y, int z) { - __nvvm_v4i16_t r; - __asm__( - "suld.b.3d.v4.b16.zero {%0, %1, %2, %3}, [%4, {%5, %6, %7, %7}];" - : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i16_to_vec(r); -} - -// NVVM Surface Load Intrinsics - v4i32 (trap/clamp/zero) -int4 __clc_llvm_nvvm_suld_1d_v4i32_trap(ulong img, int x) { - __nvvm_v4i32_t r; - __asm__("suld.b.1d.v4.b32.trap {%0, %1, %2, %3}, [%4, {%5}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_2d_v4i32_trap(ulong img, int x, int y) { - __nvvm_v4i32_t r; - __asm__("suld.b.2d.v4.b32.trap {%0, %1, %2, %3}, [%4, {%5, %6}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_3d_v4i32_trap(ulong img, int x, int y, int z) { - __nvvm_v4i32_t r; - __asm__( - "suld.b.3d.v4.b32.trap {%0, %1, %2, %3}, [%4, {%5, %6, %7, %7}];" - : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_1d_v4i32_clamp(ulong img, int x) { - __nvvm_v4i32_t r; - __asm__("suld.b.1d.v4.b32.clamp {%0, %1, %2, %3}, [%4, {%5}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_2d_v4i32_clamp(ulong img, int x, int y) { - __nvvm_v4i32_t r; - __asm__("suld.b.2d.v4.b32.clamp {%0, %1, %2, %3}, [%4, {%5, %6}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_3d_v4i32_clamp(ulong img, int x, int y, int z) { - __nvvm_v4i32_t r; - __asm__( - "suld.b.3d.v4.b32.clamp {%0, %1, %2, %3}, [%4, {%5, %6, %7, %7}];" - : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_1d_v4i32_zero(ulong img, int x) { - __nvvm_v4i32_t r; - __asm__("suld.b.1d.v4.b32.zero {%0, %1, %2, %3}, [%4, {%5}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_2d_v4i32_zero(ulong img, int x, int y) { - __nvvm_v4i32_t r; - __asm__("suld.b.2d.v4.b32.zero {%0, %1, %2, %3}, [%4, {%5, %6}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_3d_v4i32_zero(ulong img, int x, int y, int z) { - __nvvm_v4i32_t r; - __asm__( - "suld.b.3d.v4.b32.zero {%0, %1, %2, %3}, [%4, {%5, %6, %7, %7}];" - : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i32_to_vec(r); -} - -// BINDLESS IMAGES - SURFACES v2i8 and v4i8 -short2 __clc_llvm_nvvm_suld_1d_v2i8_clamp(ulong img, int x) { - __nvvm_v2i16_t r; - __asm__("suld.b.1d.v2.b8.clamp {%0, %1}, [%2, {%3}];" : "=h"(r.x), "=h"(r.y) - : "l"(img), "r"(x)); - return __nvvm_v2i16_to_vec(r); -} -short2 __clc_llvm_nvvm_suld_2d_v2i8_clamp(ulong img, int x, int y) { - __nvvm_v2i16_t r; - __asm__("suld.b.2d.v2.b8.clamp {%0, %1}, [%2, {%3, %4}];" : "=h"(r.x), "=h"(r.y) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v2i16_to_vec(r); -} -short2 __clc_llvm_nvvm_suld_3d_v2i8_clamp(ulong img, int x, int y, int z) { - __nvvm_v2i16_t r; - __asm__("suld.b.3d.v2.b8.clamp {%0, %1}, [%2, {%3, %4, %5, %5}];" : "=h"(r.x), "=h"(r.y) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v2i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_1d_v4i8_clamp(ulong img, int x) { - __nvvm_v4i16_t r; - __asm__("suld.b.1d.v4.b8.clamp {%0, %1, %2, %3}, [%4, {%5}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_2d_v4i8_clamp(ulong img, int x, int y) { - __nvvm_v4i16_t r; - __asm__("suld.b.2d.v4.b8.clamp {%0, %1, %2, %3}, [%4, {%5, %6}];" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_3d_v4i8_clamp(ulong img, int x, int y, int z) { - __nvvm_v4i16_t r; - __asm__( - "suld.b.3d.v4.b8.clamp {%0, %1, %2, %3}, [%4, {%5, %6, %7, %7}];" - : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i16_to_vec(r); -} - -// TEXTURE SAMPLING (floating-point coordinates) -int4 __clc_llvm_nvvm_tex_1d_v4i32_f32(ulong img, float x) { - __nvvm_v4i32_t r; - __asm__("tex.1d.v4.s32.f32 {%0, %1, %2, %3}, [%4, {%5}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_2d_v4i32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__( - "tex.2d.v4.s32.f32 {%0, %1, %2, %3}, [%4, {%5, %6}];" - : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_3d_v4i32_f32(ulong img, float x, float y, float z) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.3d.v4.s32.f32, (%4, %5,%6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z)); - return __nvvm_v4i32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_1d_v4j32_f32(ulong img, float x) { - __nvvm_v4u32_t r; - __asm__("tex.1d.v4.u32.f32 {%0, %1, %2, %3}, [%4, {%5}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_2d_v4j32_f32(ulong img, float x, float y) { - __nvvm_v4u32_t r; - __asm__( - "tex.2d.v4.u32.f32 {%0, %1, %2, %3}, [%4, {%5, %6}];" - : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_3d_v4j32_f32(ulong img, float x, float y, float z) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.3d.v4.u32.f32, (%4, %5,%6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z)); - return __nvvm_v4u32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_1d_v4f32_f32(ulong img, float x) { - __nvvm_v4f32_t r; - __asm__("tex.1d.v4.f32.f32 {%0, %1, %2, %3}, [%4, {%5}];" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_2d_v4f32_f32(ulong img, float x, float y) { - __nvvm_v4f32_t r; - __asm__( - "tex.2d.v4.f32.f32 {%0, %1, %2, %3}, [%4, {%5, %6}];" - : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_3d_v4f32_f32(ulong img, float x, float y, float z) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.3d.v4.f32.f32, (%4, %5,%6, %7);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z)); - return __nvvm_v4f32_to_vec(r); -} - -// TEXTURE GATHER -float4 __clc_llvm_nvvm_tld4_r_2d_v4f32_f32(ulong img, float x, float y) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.r.2d.v4f32.f32, (%4,%5, %6);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tld4_g_2d_v4f32_f32(ulong img, float x, float y) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.g.2d.v4f32.f32, (%4,%5, %6);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tld4_b_2d_v4f32_f32(ulong img, float x, float y) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.b.2d.v4f32.f32, (%4,%5, %6);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tld4_a_2d_v4f32_f32(ulong img, float x, float y) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.a.2d.v4f32.f32, (%4,%5, %6);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4f32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_r_2d_v4s32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.r.2d.v4s32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_g_2d_v4s32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.g.2d.v4s32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_b_2d_v4s32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.b.2d.v4s32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_a_2d_v4s32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.a.2d.v4s32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_r_2d_v4u32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.r.2d.v4u32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_g_2d_v4u32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.g.2d.v4u32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_b_2d_v4u32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.b.2d.v4u32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tld4_a_2d_v4u32_f32(ulong img, float x, float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), llvm.nvvm.tld4.unified.a.2d.v4u32.f32, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} - -// TEXTURE FETCHING (integer coordinates) -int4 __clc_llvm_nvvm_tex_1d_v4i32_s32(ulong img, int x) { - __nvvm_v4i32_t r; - __asm__("tex.1d.v4.s32.s32 {%0, %1, %2, %3}, [%4, {%5}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_2d_v4i32_s32(ulong img, int x, int y) { - __nvvm_v4i32_t r; - __asm__( - "tex.2d.v4.s32.s32 {%0, %1, %2, %3}, [%4, {%5, %6}];" - : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_3d_v4i32_s32(ulong img, int x, int y, int z) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.3d.v4.s32.s32, (%4, %5,%6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4i32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_1d_v4j32_s32(ulong img, int x) { - __nvvm_v4u32_t r; - __asm__("tex.1d.v4.u32.s32 {%0, %1, %2, %3}, [%4, {%5}];" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_2d_v4j32_s32(ulong img, int x, int y) { - __nvvm_v4u32_t r; - __asm__( - "tex.2d.v4.s32.s32 {%0, %1, %2, %3}, [%4, {%5, %6}];" - : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_3d_v4j32_s32(ulong img, int x, int y, int z) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.3d.v4.u32.s32, (%4, %5,%6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4u32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_1d_v4f32_s32(ulong img, int x) { - __nvvm_v4f32_t r; - __asm__("tex.1d.v4.f32.s32 {%0, %1, %2, %3}, [%4, {%5}];" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "r"(x)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_2d_v4f32_s32(ulong img, int x, int y) { - __nvvm_v4f32_t r; - __asm__( - "tex.2d.v4.f32.s32 {%0, %1, %2, %3}, [%4, {%5, %6}];" - : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "r"(x), "r"(y)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_3d_v4f32_s32(ulong img, int x, int y, int z) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.3d.v4.f32.s32, (%4, %5,%6, %7);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "r"(x), "r"(y), "r"(z)); - return __nvvm_v4f32_to_vec(r); -} - -// MIPMAP - Level -float4 __clc_llvm_nvvm_tex_1d_level_v4f32_f32(ulong img, float x, float lvl) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.1d.v4.f32.f32,(%4, %5, %6);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(lvl)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_2d_level_v4f32_f32(ulong img, float x, float y, - float lvl) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.2d.v4.f32.f32,(%4, %5, %6, %7);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(lvl)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_3d_level_v4f32_f32(ulong img, float x, float y, - float z, float lvl) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.3d.v4.f32.f32,(%4, %5, %6, %7, %8);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z), "f"(lvl)); - return __nvvm_v4f32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_1d_level_v4i32_f32(ulong img, float x, float lvl) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.1d.v4.s32.f32,(%4, %5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(lvl)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_2d_level_v4i32_f32(ulong img, float x, float y, - float lvl) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.2d.v4.s32.f32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(lvl)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_3d_level_v4i32_f32(ulong img, float x, float y, - float z, float lvl) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.3d.v4.s32.f32,(%4, %5, %6, %7, %8);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z), "f"(lvl)); - return __nvvm_v4i32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_1d_level_v4j32_f32(ulong img, float x, float lvl) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.1d.v4.u32.f32,(%4, %5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(lvl)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_2d_level_v4j32_f32(ulong img, float x, float y, - float lvl) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.2d.v4.u32.f32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(lvl)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_3d_level_v4j32_f32(ulong img, float x, float y, - float z, float lvl) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.level.3d.v4.u32.f32,(%4, %5, %6, %7, %8);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z), "f"(lvl)); - return __nvvm_v4u32_to_vec(r); -} - -// MIPMAP - Grad -float4 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32(ulong img, float x, float dX, - float dY) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.1d.v4.f32.f32,(%4, %5, %6, %7);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(dX), "f"(dY)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32(ulong img, float x, float y, - float dXx, float dXy, float dYx, - float dYy) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.2d.v4.f32.f32,(%4, %5, %6, %7, %8, %9, %10);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(dXx), "f"(dXy), "f"(dYx), "f"(dYy)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32(ulong img, float x, float y, - float z, float dXx, float dXy, - float dXz, float dYx, float dYy, - float dYz) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.3d.v4.f32.f32,(%4, %5, %6, %7, %8, %9, %10, %11, %12, %13);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z), "f"(dXx), "f"(dXy), "f"(dXz), - "f"(dYx), "f"(dYy), "f"(dYz)); - return __nvvm_v4f32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32(ulong img, float x, float dX, - float dY) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.1d.v4.s32.f32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(dX), "f"(dY)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32(ulong img, float x, float y, - float dXx, float dXy, float dYx, - float dYy) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.2d.v4.s32.f32,(%4, %5, %6, %7, %8, %9, %10);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(dXx), "f"(dXy), "f"(dYx), "f"(dYy)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32(ulong img, float x, float y, float z, - float dXx, float dXy, float dXz, - float dYx, float dYy, float dYz) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.3d.v4.s32.f32,(%4, %5, %6, %7, %8, %9, %10, %11, %12, %13);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z), "f"(dXx), "f"(dXy), "f"(dXz), - "f"(dYx), "f"(dYy), "f"(dYz)); - return __nvvm_v4i32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32(ulong img, float x, float dX, - float dY) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.1d.v4.u32.f32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(dX), "f"(dY)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32(ulong img, float x, float y, - float dXx, float dXy, float dYx, - float dYy) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.2d.v4.u32.f32,(%4, %5, %6, %7, %8, %9, %10);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(dXx), "f"(dXy), "f"(dYx), "f"(dYy)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32(ulong img, float x, float y, - float z, float dXx, float dXy, - float dXz, float dYx, float dYy, - float dYz) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.grad.3d.v4.u32.f32,(%4, %5, %6, %7, %8, %9, %10, %11, %12, %13);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z), "f"(dXx), "f"(dXy), "f"(dXz), - "f"(dYx), "f"(dYy), "f"(dYz)); - return __nvvm_v4u32_to_vec(r); -} - -// CUBEMAP -float4 __clc_llvm_nvvm_tex_cube_v4f32_f32(ulong img, float x, float y, - float z) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.cube.v4.f32.f32, (%4,%5, %6, %7);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z)); - return __nvvm_v4f32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_cube_v4i32_f32(ulong img, float x, float y, float z) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.cube.v4.s32.f32, (%4,%5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z)); - return __nvvm_v4i32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_cube_v4j32_f32(ulong img, float x, float y, float z) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.cube.v4.u32.f32, (%4,%5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "f"(x), "f"(y), "f"(z)); - return __nvvm_v4u32_to_vec(r); -} - -// SURFACE ARRAY LOADS -short2 __clc_llvm_nvvm_suld_1d_array_v2i8_clamp(ulong img, int idx, int x) { - __nvvm_v2i16_t r; - __asm__("suld.b.a1d.v2.b8.clamp {%0, %1}, [%2, {%3, %4}];" : "=h"(r.x), "=h"(r.y) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v2i16_to_vec(r); -} -short2 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp(ulong img, int idx, int x, - int y) { - __nvvm_v2i16_t r; - __asm__("suld.b.a2d.v2.b8.clamp {%0, %1}, [%2, {%3, %4, %5}];" : "=h"(r.x), "=h"(r.y) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v2i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_1d_array_v4i8_clamp(ulong img, int idx, int x) { - __nvvm_v4i16_t r; - __asm__( - "suld.b.a1d.v4.b8.clamp {%0, %1, %2, %3}, [%4, {%5, %6}];" - : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp(ulong img, int idx, int x, - int y) { - __nvvm_v4i16_t r; - __asm__("call (%0, %1, %2, %3), suld.b.a2d.v4.b8.clamp, (%4, %5,%6, %7);" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v4i16_to_vec(r); -} -short2 __clc_llvm_nvvm_suld_1d_array_v2i16_clamp(ulong img, int idx, int x) { - __nvvm_v2i16_t r; - __asm__("suld.b.a1d.v2.b16.clamp {%0, %1}, [%2, {%3, %4}];" : "=h"(r.x), "=h"(r.y) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v2i16_to_vec(r); -} -short2 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp(ulong img, int idx, int x, - int y) { - __nvvm_v2i16_t r; - __asm__( - "suld.b.a2d.v2.b16.clamp {%0, %1}, [%2, {%3, %4, %5}];" - : "=h"(r.x), "=h"(r.y) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v2i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_1d_array_v4i16_clamp(ulong img, int idx, int x) { - __nvvm_v4i16_t r; - __asm__("call (%0, %1, %2, %3), suld.b.a1d.v4.b16.clamp, (%4,%5, %6);" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v4i16_to_vec(r); -} -short4 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp(ulong img, int idx, int x, - int y) { - __nvvm_v4i16_t r; - __asm__("call (%0, %1, %2, %3), suld.b.a2d.v4.b16.clamp, (%4,%5, %6, %7);" : "=h"(r.x), "=h"(r.y), "=h"(r.z), "=h"(r.w) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v4i16_to_vec(r); -} -int2 __clc_llvm_nvvm_suld_1d_array_v2i32_clamp(ulong img, int idx, int x) { - __nvvm_v2i32_t r; - __asm__("suld.b.a1d.v2.b32.clamp {%0, %1}, [%2, {%3, %4}];" : "=r"(r.x), "=r"(r.y) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v2i32_to_vec(r); -} -int2 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp(ulong img, int idx, int x, - int y) { - __nvvm_v2i32_t r; - __asm__( - "suld.b.a2d.v2.b32.clamp {%0, %1}, [%2, {%3, %4, %5}];" - : "=r"(r.x), "=r"(r.y) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v2i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_1d_array_v4i32_clamp(ulong img, int idx, int x) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), suld.b.a1d.v4.b32.clamp, (%4,%5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp(ulong img, int idx, int x, - int y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), suld.b.a2d.v4.b32.clamp, (%4,%5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v4i32_to_vec(r); -} - -// TEXTURE ARRAY - float coords -float4 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32(ulong img, int idx, - float x) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.a1d.v4.f32.f32,(%4, %5, %6);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "r"(idx), "f"(x)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32(ulong img, int idx, - float x, float y) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.a2d.v4.f32.f32,(%4, %5, %6, %7);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "r"(idx), "f"(x), "f"(y)); - return __nvvm_v4f32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32(ulong img, int idx, - float x) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.a1d.v4.s32.f32,(%4, %5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "f"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32(ulong img, int idx, float x, - float y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.a2d.v4.s32.f32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "f"(x), "f"(y)); - return __nvvm_v4i32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32(ulong img, int idx, - float x) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.a1d.v4.u32.f32,(%4, %5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "f"(x)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32(ulong img, int idx, - float x, float y) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.a2d.v4.u32.f32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "f"(x), "f"(y)); - return __nvvm_v4u32_to_vec(r); -} - -// TEXTURE ARRAY - int coords -float4 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32(ulong img, int idx, - int x) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.a1d.v4.f32.s32,(%4, %5, %6);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v4f32_to_vec(r); -} -float4 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32(ulong img, int idx, int x, - int y) { - __nvvm_v4f32_t r; - __asm__("call (%0, %1, %2, %3), tex.a2d.v4.f32.s32,(%4, %5, %6, %7);" : "=f"(r.x), "=f"(r.y), "=f"(r.z), "=f"(r.w) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v4f32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32(ulong img, int idx, int x) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.a1d.v4.s32.s32,(%4, %5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v4i32_to_vec(r); -} -int4 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32(ulong img, int idx, int x, - int y) { - __nvvm_v4i32_t r; - __asm__("call (%0, %1, %2, %3), tex.a2d.v4.s32.s32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v4i32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32(ulong img, int idx, - int x) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.a1d.v4.u32.s32,(%4, %5, %6);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "r"(x)); - return __nvvm_v4u32_to_vec(r); -} -uint4 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32(ulong img, int idx, int x, - int y) { - __nvvm_v4u32_t r; - __asm__("call (%0, %1, %2, %3), tex.a2d.v4.u32.s32,(%4, %5, %6, %7);" : "=r"(r.x), "=r"(r.y), "=r"(r.z), "=r"(r.w) - : "l"(img), "r"(idx), "r"(x), "r"(y)); - return __nvvm_v4u32_to_vec(r); -} diff --git a/libclc/libspirv/lib/ptx-nvidiacl/images/image_helpers.ll.s b/libclc/libspirv/lib/ptx-nvidiacl/images/image_helpers.ll.s deleted file mode 100644 index 2e20ce0feb5eb..0000000000000 --- a/libclc/libspirv/lib/ptx-nvidiacl/images/image_helpers.ll.s +++ /dev/null @@ -1,3168 +0,0 @@ -// -// Generated by LLVM NVPTX Back-End -// - -.version 6.3 -.target sm_75 -.address_size 32 - - // .globl __clc__sampled_image_unpack_image // -- Begin function __clc__sampled_image_unpack_image - // @__clc__sampled_image_unpack_image -.visible .func (.param .b64 func_retval0) __clc__sampled_image_unpack_image( - .param .b64 __clc__sampled_image_unpack_image_param_0, - .param .b32 __clc__sampled_image_unpack_image_param_1 -) -{ - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc__sampled_image_unpack_image_param_0]; - st.param.b64 [func_retval0], %rd1; - ret; - // -- End function -} - // .globl __clc__sampled_image_unpack_sampler // -- Begin function __clc__sampled_image_unpack_sampler -.visible .func (.param .b32 func_retval0) __clc__sampled_image_unpack_sampler( - .param .b64 __clc__sampled_image_unpack_sampler_param_0, - .param .b32 __clc__sampled_image_unpack_sampler_param_1 -) // @__clc__sampled_image_unpack_sampler -{ - .reg .b32 %r<2>; - -// %bb.0: // %entry - ld.param.b32 %r1, [__clc__sampled_image_unpack_sampler_param_1]; - st.param.b32 [func_retval0], %r1; - ret; - // -- End function -} - // .globl __clc__sampled_image_pack // -- Begin function __clc__sampled_image_pack -.visible .func (.param .align 8 .b8 func_retval0[16]) __clc__sampled_image_pack( - .param .b64 __clc__sampled_image_pack_param_0, - .param .b32 __clc__sampled_image_pack_param_1 -) // @__clc__sampled_image_pack -{ - .reg .b32 %r<2>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc__sampled_image_pack_param_0]; - ld.param.b32 %r1, [__clc__sampled_image_pack_param_1]; - st.param.b32 [func_retval0+8], %r1; - st.param.b64 [func_retval0], %rd1; - ret; - // -- End function -} - // .globl __clc__sampler_extract_normalized_coords_prop // -- Begin function __clc__sampler_extract_normalized_coords_prop -.visible .func (.param .b32 func_retval0) __clc__sampler_extract_normalized_coords_prop( - .param .b32 __clc__sampler_extract_normalized_coords_prop_param_0 -) // @__clc__sampler_extract_normalized_coords_prop -{ - .reg .b32 %r<3>; - -// %bb.0: // %entry - ld.param.b32 %r1, [__clc__sampler_extract_normalized_coords_prop_param_0]; - and.b32 %r2, %r1, 1; - st.param.b32 [func_retval0], %r2; - ret; - // -- End function -} - // .globl __clc__sampler_extract_filter_mode_prop // -- Begin function __clc__sampler_extract_filter_mode_prop -.visible .func (.param .b32 func_retval0) __clc__sampler_extract_filter_mode_prop( - .param .b32 __clc__sampler_extract_filter_mode_prop_param_0 -) // @__clc__sampler_extract_filter_mode_prop -{ - .reg .b32 %r<3>; - -// %bb.0: // %entry - ld.param.b32 %r1, [__clc__sampler_extract_filter_mode_prop_param_0]; - bfe.u32 %r2, %r1, 1, 1; - st.param.b32 [func_retval0], %r2; - ret; - // -- End function -} - // .globl __clc__sampler_extract_addressing_mode_prop // -- Begin function __clc__sampler_extract_addressing_mode_prop -.visible .func (.param .b32 func_retval0) __clc__sampler_extract_addressing_mode_prop( - .param .b32 __clc__sampler_extract_addressing_mode_prop_param_0 -) // @__clc__sampler_extract_addressing_mode_prop -{ - .reg .b32 %r<3>; - -// %bb.0: // %entry - ld.param.b32 %r1, [__clc__sampler_extract_addressing_mode_prop_param_0]; - shr.u32 %r2, %r1, 2; - st.param.b32 [func_retval0], %r2; - ret; - // -- End function -} - // .globl __clc_struct32_to_vector // -- Begin function __clc_struct32_to_vector -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_struct32_to_vector( - .param .align 4 .b8 __clc_struct32_to_vector_param_0[16] -) // @__clc_struct32_to_vector -{ - .reg .b32 %r<5>; - -// %bb.0: - ld.param.b32 %r1, [__clc_struct32_to_vector_param_0+12]; - ld.param.b32 %r2, [__clc_struct32_to_vector_param_0+8]; - ld.param.b32 %r3, [__clc_struct32_to_vector_param_0+4]; - ld.param.b32 %r4, [__clc_struct32_to_vector_param_0]; - st.param.v4.b32 [func_retval0], {%r4, %r3, %r2, %r1}; - ret; - // -- End function -} - // .globl __clc_struct32_to_vector2 // -- Begin function __clc_struct32_to_vector2 -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_struct32_to_vector2( - .param .align 4 .b8 __clc_struct32_to_vector2_param_0[8] -) // @__clc_struct32_to_vector2 -{ - .reg .b32 %r<3>; - -// %bb.0: - ld.param.b32 %r1, [__clc_struct32_to_vector2_param_0+4]; - ld.param.b32 %r2, [__clc_struct32_to_vector2_param_0]; - st.param.v2.b32 [func_retval0], {%r2, %r1}; - ret; - // -- End function -} - // .globl __clc_structf32_to_vector // -- Begin function __clc_structf32_to_vector -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_structf32_to_vector( - .param .align 4 .b8 __clc_structf32_to_vector_param_0[16] -) // @__clc_structf32_to_vector -{ - .reg .b32 %r<5>; - -// %bb.0: - ld.param.b32 %r1, [__clc_structf32_to_vector_param_0+12]; - ld.param.b32 %r2, [__clc_structf32_to_vector_param_0+8]; - ld.param.b32 %r3, [__clc_structf32_to_vector_param_0+4]; - ld.param.b32 %r4, [__clc_structf32_to_vector_param_0]; - st.param.v4.b32 [func_retval0], {%r4, %r3, %r2, %r1}; - ret; - // -- End function -} - // .globl __clc_struct16_to_vector // -- Begin function __clc_struct16_to_vector -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_struct16_to_vector( - .param .align 2 .b8 __clc_struct16_to_vector_param_0[8] -) // @__clc_struct16_to_vector -{ - .reg .b16 %rs<5>; - -// %bb.0: - ld.param.b16 %rs1, [__clc_struct16_to_vector_param_0+6]; - ld.param.b16 %rs2, [__clc_struct16_to_vector_param_0+4]; - ld.param.b16 %rs3, [__clc_struct16_to_vector_param_0+2]; - ld.param.b16 %rs4, [__clc_struct16_to_vector_param_0]; - st.param.v4.b16 [func_retval0], {%rs4, %rs3, %rs2, %rs1}; - ret; - // -- End function -} - // .globl __clc_struct16_to_vector2 // -- Begin function __clc_struct16_to_vector2 -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_struct16_to_vector2( - .param .align 2 .b8 __clc_struct16_to_vector2_param_0[4] -) // @__clc_struct16_to_vector2 -{ - .reg .b16 %rs<3>; - -// %bb.0: - ld.param.b16 %rs1, [__clc_struct16_to_vector2_param_0+2]; - ld.param.b16 %rs2, [__clc_struct16_to_vector2_param_0]; - st.param.v2.b16 [func_retval0], {%rs2, %rs1}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i16_trap // -- Begin function __clc_llvm_nvvm_suld_1d_v4i16_trap -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i16_trap( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i16_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i16_trap_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i16_trap -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i16_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i16_trap_param_1]; - suld.b.1d.v4.b16.trap {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - { // callseq 0, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r2, %r3}, [retval0]; - } // callseq 0 - st.param.v2.b32 [func_retval0], {%r2, %r3}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i16_trap // -- Begin function __clc_llvm_nvvm_suld_2d_v4i16_trap -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i16_trap( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i16_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_trap_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i16_trap -{ - .reg .b16 %rs<5>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i16_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i16_trap_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i16_trap_param_2]; - suld.b.2d.v4.b16.trap {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - { // callseq 1, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r3, %r4}, [retval0]; - } // callseq 1 - st.param.v2.b32 [func_retval0], {%r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i16_trap // -- Begin function __clc_llvm_nvvm_suld_3d_v4i16_trap -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i16_trap( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_trap_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i16_trap -{ - .reg .b16 %rs<5>; - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i16_trap_param_3]; - suld.b.3d.v4.b16.trap {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 2, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r4, %r5}, [retval0]; - } // callseq 2 - st.param.v2.b32 [func_retval0], {%r4, %r5}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i16_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i16_clamp_param_1]; - suld.b.1d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - { // callseq 3, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r2, %r3}, [retval0]; - } // callseq 3 - st.param.v2.b32 [func_retval0], {%r2, %r3}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i16_clamp_param_2]; - suld.b.2d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - { // callseq 4, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r3, %r4}, [retval0]; - } // callseq 4 - st.param.v2.b32 [func_retval0], {%r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i16_clamp_param_3]; - suld.b.3d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 5, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r4, %r5}, [retval0]; - } // callseq 5 - st.param.v2.b32 [func_retval0], {%r4, %r5}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i16_zero // -- Begin function __clc_llvm_nvvm_suld_1d_v4i16_zero -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i16_zero( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i16_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i16_zero_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i16_zero -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i16_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i16_zero_param_1]; - suld.b.1d.v4.b16.zero {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - { // callseq 6, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r2, %r3}, [retval0]; - } // callseq 6 - st.param.v2.b32 [func_retval0], {%r2, %r3}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i16_zero // -- Begin function __clc_llvm_nvvm_suld_2d_v4i16_zero -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i16_zero( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i16_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i16_zero_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i16_zero -{ - .reg .b16 %rs<5>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i16_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i16_zero_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i16_zero_param_2]; - suld.b.2d.v4.b16.zero {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - { // callseq 7, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r3, %r4}, [retval0]; - } // callseq 7 - st.param.v2.b32 [func_retval0], {%r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i16_zero // -- Begin function __clc_llvm_nvvm_suld_3d_v4i16_zero -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i16_zero( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i16_zero_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i16_zero -{ - .reg .b16 %rs<5>; - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i16_zero_param_3]; - suld.b.3d.v4.b16.zero {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 8, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r4, %r5}, [retval0]; - } // callseq 8 - st.param.v2.b32 [func_retval0], {%r4, %r5}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i32_trap // -- Begin function __clc_llvm_nvvm_suld_1d_v4i32_trap -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_v4i32_trap( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i32_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i32_trap_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i32_trap -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i32_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i32_trap_param_1]; - suld.b.1d.v4.b32.trap {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 9, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 9 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i32_trap // -- Begin function __clc_llvm_nvvm_suld_2d_v4i32_trap -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_v4i32_trap( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i32_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_trap_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i32_trap -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i32_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i32_trap_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i32_trap_param_2]; - suld.b.2d.v4.b32.trap {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 10, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 10 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i32_trap // -- Begin function __clc_llvm_nvvm_suld_3d_v4i32_trap -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_3d_v4i32_trap( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_trap_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i32_trap -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i32_trap_param_3]; - suld.b.3d.v4.b32.trap {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 11, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 11 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i32_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i32_clamp -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i32_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i32_clamp_param_1]; - suld.b.1d.v4.b32.clamp {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 12, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 12 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i32_clamp -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i32_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i32_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i32_clamp_param_2]; - suld.b.2d.v4.b32.clamp {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 13, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 13 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_3d_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i32_clamp -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i32_clamp_param_3]; - suld.b.3d.v4.b32.clamp {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 14, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 14 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i32_zero // -- Begin function __clc_llvm_nvvm_suld_1d_v4i32_zero -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_v4i32_zero( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i32_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i32_zero_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i32_zero -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i32_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i32_zero_param_1]; - suld.b.1d.v4.b32.zero {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 15, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 15 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i32_zero // -- Begin function __clc_llvm_nvvm_suld_2d_v4i32_zero -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_v4i32_zero( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i32_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i32_zero_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i32_zero -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i32_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i32_zero_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i32_zero_param_2]; - suld.b.2d.v4.b32.zero {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 16, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 16 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i32_zero // -- Begin function __clc_llvm_nvvm_suld_3d_v4i32_zero -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_3d_v4i32_zero( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i32_zero_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i32_zero -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i32_zero_param_3]; - suld.b.3d.v4.b32.zero {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 17, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 17 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_1d_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v2i8_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<3>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v2i8_clamp_param_1]; - suld.b.1d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1}]; - { // callseq 18, 0 - .param .align 2 .b8 param0[4]; - .param .align 4 .b8 retval0[4]; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector2, (param0); - ld.param.b32 %r2, [retval0]; - } // callseq 18 - st.param.b32 [func_retval0], %r2; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_2d_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v2i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v2i8_clamp_param_2]; - suld.b.2d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2}]; - { // callseq 19, 0 - .param .align 2 .b8 param0[4]; - .param .align 4 .b8 retval0[4]; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector2, (param0); - ld.param.b32 %r3, [retval0]; - } // callseq 19 - st.param.b32 [func_retval0], %r3; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_3d_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v2i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v2i8_clamp_param_3]; - suld.b.3d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 20, 0 - .param .align 2 .b8 param0[4]; - .param .align 4 .b8 retval0[4]; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector2, (param0); - ld.param.b32 %r4, [retval0]; - } // callseq 20 - st.param.b32 [func_retval0], %r4; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_v4i8_clamp_param_1 -) // @__clc_llvm_nvvm_suld_1d_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_v4i8_clamp_param_1]; - suld.b.1d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1}]; - { // callseq 21, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r2, %r3}, [retval0]; - } // callseq 21 - st.param.v2.b32 [func_retval0], {%r2, %r3}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_v4i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_2d_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_v4i8_clamp_param_2]; - suld.b.2d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - { // callseq 22, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r3, %r4}, [retval0]; - } // callseq 22 - st.param.v2.b32 [func_retval0], {%r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_3d_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_3d_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_3d_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_3d_v4i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_3d_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_3d_v4i8_clamp_param_3]; - suld.b.3d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 23, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r4, %r5}, [retval0]; - } // callseq 23 - st.param.v2.b32 [func_retval0], {%r4, %r5}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4i32_f32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4i32_f32 -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_v4i32_f32_param_1]; - tex.1d.v4.s32.f32 {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 24, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 24 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_f32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4i32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_v4i32_f32_param_2]; - tex.2d.v4.s32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 25, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 25 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4i32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_v4i32_f32_param_3]; - tex.3d.v4.s32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 26, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 26 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4j32_f32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4j32_f32 -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_v4j32_f32_param_1]; - tex.1d.v4.u32.f32 {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 27, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 27 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_f32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4j32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_v4j32_f32_param_2]; - tex.2d.v4.u32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 28, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 28 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4j32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_v4j32_f32_param_3]; - tex.3d.v4.u32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 29, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 29 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4f32_f32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4f32_f32 -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_v4f32_f32_param_1]; - tex.1d.v4.f32.f32 {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 30, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 30 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_v4f32_f32_param_2]; - tex.2d.v4.f32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 31, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 31 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4f32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_v4f32_f32_param_3]; - tex.3d.v4.f32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 32, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 32 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_r_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_r_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_r_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_r_2d_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_r_2d_v4f32_f32_param_2]; - tld4.r.2d.v4.f32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 33, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 33 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_g_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_g_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_g_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_g_2d_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_g_2d_v4f32_f32_param_2]; - tld4.g.2d.v4.f32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 34, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 34 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_b_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_b_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_b_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_b_2d_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_b_2d_v4f32_f32_param_2]; - tld4.b.2d.v4.f32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 35, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 35 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_a_2d_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tld4_a_2d_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_a_2d_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_a_2d_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_a_2d_v4f32_f32_param_2]; - tld4.a.2d.v4.f32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 36, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 36 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_r_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_r_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_r_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_r_2d_v4s32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_r_2d_v4s32_f32_param_2]; - tld4.r.2d.v4.s32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 37, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 37 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_g_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_g_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_g_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_g_2d_v4s32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_g_2d_v4s32_f32_param_2]; - tld4.g.2d.v4.s32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 38, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 38 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_b_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_b_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_b_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_b_2d_v4s32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_b_2d_v4s32_f32_param_2]; - tld4.b.2d.v4.s32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 39, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 39 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_a_2d_v4s32_f32 // -- Begin function __clc_llvm_nvvm_tld4_a_2d_v4s32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_a_2d_v4s32_f32( - .param .b64 __clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_a_2d_v4s32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_a_2d_v4s32_f32_param_2]; - tld4.a.2d.v4.s32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 40, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 40 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_r_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_r_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_r_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_r_2d_v4u32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_r_2d_v4u32_f32_param_2]; - tld4.r.2d.v4.u32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 41, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 41 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_g_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_g_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_g_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_g_2d_v4u32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_g_2d_v4u32_f32_param_2]; - tld4.g.2d.v4.u32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 42, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 42 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_b_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_b_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_b_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_b_2d_v4u32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_b_2d_v4u32_f32_param_2]; - tld4.b.2d.v4.u32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 43, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 43 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tld4_a_2d_v4u32_f32 // -- Begin function __clc_llvm_nvvm_tld4_a_2d_v4u32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tld4_a_2d_v4u32_f32( - .param .b64 __clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_2 -) // @__clc_llvm_nvvm_tld4_a_2d_v4u32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tld4_a_2d_v4u32_f32_param_2]; - tld4.a.2d.v4.u32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 44, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 44 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4i32_s32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4i32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4i32_s32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4i32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4i32_s32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4i32_s32 -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4i32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_v4i32_s32_param_1]; - tex.1d.v4.s32.s32 {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 45, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 45 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4i32_s32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4i32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4i32_s32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4i32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4i32_s32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4i32_s32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4i32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_v4i32_s32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_v4i32_s32_param_2]; - tex.2d.v4.s32.s32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 46, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 46 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4i32_s32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4i32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4i32_s32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4i32_s32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4i32_s32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_v4i32_s32_param_3]; - tex.3d.v4.s32.s32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 47, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 47 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4j32_s32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4j32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4j32_s32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4j32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4j32_s32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4j32_s32 -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4j32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_v4j32_s32_param_1]; - tex.1d.v4.u32.s32 {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 48, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 48 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4j32_s32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4j32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4j32_s32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4j32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4j32_s32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4j32_s32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4j32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_v4j32_s32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_v4j32_s32_param_2]; - tex.2d.v4.u32.s32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 49, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 49 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4j32_s32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4j32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4j32_s32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4j32_s32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4j32_s32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_v4j32_s32_param_3]; - tex.3d.v4.u32.s32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 50, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 50 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_v4f32_s32 // -- Begin function __clc_llvm_nvvm_tex_1d_v4f32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_v4f32_s32( - .param .b64 __clc_llvm_nvvm_tex_1d_v4f32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_v4f32_s32_param_1 -) // @__clc_llvm_nvvm_tex_1d_v4f32_s32 -{ - .reg .b32 %r<10>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_v4f32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_v4f32_s32_param_1]; - tex.1d.v4.f32.s32 {%r2, %r3, %r4, %r5}, [%rd1, {%r1}]; - { // callseq 51, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r5; - st.param.b32 [param0+8], %r4; - st.param.b32 [param0+4], %r3; - st.param.b32 [param0], %r2; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [retval0]; - } // callseq 51 - st.param.v4.b32 [func_retval0], {%r6, %r7, %r8, %r9}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_v4f32_s32 // -- Begin function __clc_llvm_nvvm_tex_2d_v4f32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_v4f32_s32( - .param .b64 __clc_llvm_nvvm_tex_2d_v4f32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_v4f32_s32_param_2 -) // @__clc_llvm_nvvm_tex_2d_v4f32_s32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_v4f32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_v4f32_s32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_v4f32_s32_param_2]; - tex.2d.v4.f32.s32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 52, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 52 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_v4f32_s32 // -- Begin function __clc_llvm_nvvm_tex_3d_v4f32_s32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_v4f32_s32( - .param .b64 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_v4f32_s32_param_3 -) // @__clc_llvm_nvvm_tex_3d_v4f32_s32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_v4f32_s32_param_3]; - tex.3d.v4.f32.s32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 53, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 53 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_level_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_level_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_level_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tex_1d_level_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_1d_level_v4f32_f32_param_2]; - tex.level.1d.v4.f32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1}], %r2; - { // callseq 54, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 54 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_level_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_level_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_level_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_2d_level_v4f32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_2d_level_v4f32_f32_param_3]; - tex.level.2d.v4.f32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2}], %r3; - { // callseq 55, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 55 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_level_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_level_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_level_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_4 -) // @__clc_llvm_nvvm_tex_3d_level_v4f32_f32 -{ - .reg .b32 %r<13>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_3d_level_v4f32_f32_param_4]; - tex.level.3d.v4.f32.f32 {%r5, %r6, %r7, %r8}, [%rd1, {%r1, %r2, %r3, %r3}], %r4; - { // callseq 56, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r8; - st.param.b32 [param0+8], %r7; - st.param.b32 [param0+4], %r6; - st.param.b32 [param0], %r5; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [retval0]; - } // callseq 56 - st.param.v4.b32 [func_retval0], {%r9, %r10, %r11, %r12}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_level_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_level_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_level_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_2 -) // @__clc_llvm_nvvm_tex_1d_level_v4i32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_1d_level_v4i32_f32_param_2]; - tex.level.1d.v4.s32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1}], %r2; - { // callseq 57, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 57 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_level_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_level_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_level_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_2d_level_v4i32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_2d_level_v4i32_f32_param_3]; - tex.level.2d.v4.s32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2}], %r3; - { // callseq 58, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 58 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_level_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_level_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_level_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_4 -) // @__clc_llvm_nvvm_tex_3d_level_v4i32_f32 -{ - .reg .b32 %r<13>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_3d_level_v4i32_f32_param_4]; - tex.level.3d.v4.s32.f32 {%r5, %r6, %r7, %r8}, [%rd1, {%r1, %r2, %r3, %r3}], %r4; - { // callseq 59, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r8; - st.param.b32 [param0+8], %r7; - st.param.b32 [param0+4], %r6; - st.param.b32 [param0], %r5; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [retval0]; - } // callseq 59 - st.param.v4.b32 [func_retval0], {%r9, %r10, %r11, %r12}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_level_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_level_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_level_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_2 -) // @__clc_llvm_nvvm_tex_1d_level_v4j32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_1d_level_v4j32_f32_param_2]; - tex.level.1d.v4.u32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1}], %r2; - { // callseq 60, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 60 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_level_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_level_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_level_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_2d_level_v4j32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_2d_level_v4j32_f32_param_3]; - tex.level.2d.v4.u32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2}], %r3; - { // callseq 61, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 61 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_level_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_level_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_level_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_4 -) // @__clc_llvm_nvvm_tex_3d_level_v4j32_f32 -{ - .reg .b32 %r<13>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_3d_level_v4j32_f32_param_4]; - tex.level.3d.v4.u32.f32 {%r5, %r6, %r7, %r8}, [%rd1, {%r1, %r2, %r3, %r3}], %r4; - { // callseq 62, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r8; - st.param.b32 [param0+8], %r7; - st.param.b32 [param0+4], %r6; - st.param.b32 [param0], %r5; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [retval0]; - } // callseq 62 - st.param.v4.b32 [func_retval0], {%r9, %r10, %r11, %r12}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_grad_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_grad_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_grad_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_1d_grad_v4f32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_1d_grad_v4f32_f32_param_3]; - tex.grad.1d.v4.f32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1}], {%r2}, {%r3}; - { // callseq 63, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 63 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_grad_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_grad_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_grad_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_6 -) // @__clc_llvm_nvvm_tex_2d_grad_v4f32_f32 -{ - .reg .b32 %r<15>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_4]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_5]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_grad_v4f32_f32_param_6]; - tex.grad.2d.v4.f32.f32 {%r7, %r8, %r9, %r10}, [%rd1, {%r1, %r2}], {%r3, %r4}, {%r5, %r6}; - { // callseq 64, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r10; - st.param.b32 [param0+8], %r9; - st.param.b32 [param0+4], %r8; - st.param.b32 [param0], %r7; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r11, %r12, %r13, %r14}, [retval0]; - } // callseq 64 - st.param.v4.b32 [func_retval0], {%r11, %r12, %r13, %r14}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_grad_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_grad_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_grad_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_6, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_7, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_8, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_9 -) // @__clc_llvm_nvvm_tex_3d_grad_v4f32_f32 -{ - .reg .b32 %r<18>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_4]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_5]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_6]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_7]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_8]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_3d_grad_v4f32_f32_param_9]; - tex.grad.3d.v4.f32.f32 {%r10, %r11, %r12, %r13}, [%rd1, {%r1, %r2, %r3, %r3}], {%r4, %r5, %r6, %r6}, {%r7, %r8, %r9, %r9}; - { // callseq 65, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r13; - st.param.b32 [param0+8], %r12; - st.param.b32 [param0+4], %r11; - st.param.b32 [param0], %r10; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r14, %r15, %r16, %r17}, [retval0]; - } // callseq 65 - st.param.v4.b32 [func_retval0], {%r14, %r15, %r16, %r17}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_grad_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_grad_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_grad_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_1d_grad_v4i32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_1d_grad_v4i32_f32_param_3]; - tex.grad.1d.v4.s32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1}], {%r2}, {%r3}; - { // callseq 66, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 66 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_grad_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_grad_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_grad_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_6 -) // @__clc_llvm_nvvm_tex_2d_grad_v4i32_f32 -{ - .reg .b32 %r<15>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_4]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_5]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_grad_v4i32_f32_param_6]; - tex.grad.2d.v4.s32.f32 {%r7, %r8, %r9, %r10}, [%rd1, {%r1, %r2}], {%r3, %r4}, {%r5, %r6}; - { // callseq 67, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r10; - st.param.b32 [param0+8], %r9; - st.param.b32 [param0+4], %r8; - st.param.b32 [param0], %r7; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r11, %r12, %r13, %r14}, [retval0]; - } // callseq 67 - st.param.v4.b32 [func_retval0], {%r11, %r12, %r13, %r14}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_grad_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_grad_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_grad_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_6, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_7, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_8, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_9 -) // @__clc_llvm_nvvm_tex_3d_grad_v4i32_f32 -{ - .reg .b32 %r<18>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_4]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_5]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_6]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_7]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_8]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_3d_grad_v4i32_f32_param_9]; - tex.grad.3d.v4.s32.f32 {%r10, %r11, %r12, %r13}, [%rd1, {%r1, %r2, %r3, %r3}], {%r4, %r5, %r6, %r6}, {%r7, %r8, %r9, %r9}; - { // callseq 68, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r13; - st.param.b32 [param0+8], %r12; - st.param.b32 [param0+4], %r11; - st.param.b32 [param0], %r10; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r14, %r15, %r16, %r17}, [retval0]; - } // callseq 68 - st.param.v4.b32 [func_retval0], {%r14, %r15, %r16, %r17}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_1d_grad_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_1d_grad_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_1d_grad_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_1d_grad_v4j32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_1d_grad_v4j32_f32_param_3]; - tex.grad.1d.v4.u32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1}], {%r2}, {%r3}; - { // callseq 69, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 69 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_2d_grad_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_2d_grad_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_2d_grad_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_6 -) // @__clc_llvm_nvvm_tex_2d_grad_v4j32_f32 -{ - .reg .b32 %r<15>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_4]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_5]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_2d_grad_v4j32_f32_param_6]; - tex.grad.2d.v4.u32.f32 {%r7, %r8, %r9, %r10}, [%rd1, {%r1, %r2}], {%r3, %r4}, {%r5, %r6}; - { // callseq 70, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r10; - st.param.b32 [param0+8], %r9; - st.param.b32 [param0+4], %r8; - st.param.b32 [param0], %r7; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r11, %r12, %r13, %r14}, [retval0]; - } // callseq 70 - st.param.v4.b32 [func_retval0], {%r11, %r12, %r13, %r14}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_3d_grad_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_3d_grad_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_3d_grad_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_3, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_4, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_5, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_6, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_7, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_8, - .param .b32 __clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_9 -) // @__clc_llvm_nvvm_tex_3d_grad_v4j32_f32 -{ - .reg .b32 %r<18>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_3]; - ld.param.b32 %r4, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_4]; - ld.param.b32 %r5, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_5]; - ld.param.b32 %r6, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_6]; - ld.param.b32 %r7, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_7]; - ld.param.b32 %r8, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_8]; - ld.param.b32 %r9, [__clc_llvm_nvvm_tex_3d_grad_v4j32_f32_param_9]; - tex.grad.3d.v4.u32.f32 {%r10, %r11, %r12, %r13}, [%rd1, {%r1, %r2, %r3, %r3}], {%r4, %r5, %r6, %r6}, {%r7, %r8, %r9, %r9}; - { // callseq 71, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r13; - st.param.b32 [param0+8], %r12; - st.param.b32 [param0+4], %r11; - st.param.b32 [param0], %r10; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r14, %r15, %r16, %r17}, [retval0]; - } // callseq 71 - st.param.v4.b32 [func_retval0], {%r14, %r15, %r16, %r17}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_1d_array_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v2i8_clamp_param_2]; - suld.b.a1d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2}]; - { // callseq 72, 0 - .param .align 2 .b8 param0[4]; - .param .align 4 .b8 retval0[4]; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector2, (param0); - ld.param.b32 %r3, [retval0]; - } // callseq 72 - st.param.b32 [func_retval0], %r3; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v2i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v2i8_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_2d_array_v2i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v2i8_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v2i8_clamp_param_3]; - suld.b.a2d.v2.b8.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 73, 0 - .param .align 2 .b8 param0[4]; - .param .align 4 .b8 retval0[4]; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector2, (param0); - ld.param.b32 %r4, [retval0]; - } // callseq 73 - st.param.b32 [func_retval0], %r4; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_array_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v4i8_clamp_param_2]; - suld.b.a1d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - { // callseq 74, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r3, %r4}, [retval0]; - } // callseq 74 - st.param.v2.b32 [func_retval0], {%r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v4i8_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v4i8_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_array_v4i8_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v4i8_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v4i8_clamp_param_3]; - suld.b.a2d.v4.b8.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 75, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r4, %r5}, [retval0]; - } // callseq 75 - st.param.v2.b32 [func_retval0], {%r4, %r5}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v2i16_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v2i16_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_1d_array_v2i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v2i16_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<4>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v2i16_clamp_param_2]; - suld.b.a1d.v2.b16.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2}]; - { // callseq 76, 0 - .param .align 2 .b8 param0[4]; - .param .align 4 .b8 retval0[4]; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector2, (param0); - ld.param.b32 %r3, [retval0]; - } // callseq 76 - st.param.b32 [func_retval0], %r3; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v2i16_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v2i16_clamp -.visible .func (.param .align 4 .b8 func_retval0[4]) __clc_llvm_nvvm_suld_2d_array_v2i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v2i16_clamp -{ - .reg .b16 %rs<3>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v2i16_clamp_param_3]; - suld.b.a2d.v2.b16.clamp {%rs1, %rs2}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 77, 0 - .param .align 2 .b8 param0[4]; - .param .align 4 .b8 retval0[4]; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector2, (param0); - ld.param.b32 %r4, [retval0]; - } // callseq 77 - st.param.b32 [func_retval0], %r4; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_array_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<5>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v4i16_clamp_param_2]; - suld.b.a1d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2}]; - { // callseq 78, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r3, %r4}, [retval0]; - } // callseq 78 - st.param.v2.b32 [func_retval0], {%r3, %r4}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v4i16_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v4i16_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_array_v4i16_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v4i16_clamp -{ - .reg .b16 %rs<5>; - .reg .b32 %r<6>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v4i16_clamp_param_3]; - suld.b.a2d.v4.b16.clamp {%rs1, %rs2, %rs3, %rs4}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 79, 0 - .param .align 2 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b16 [param0+6], %rs4; - st.param.b16 [param0+4], %rs3; - st.param.b16 [param0+2], %rs2; - st.param.b16 [param0], %rs1; - call.uni (retval0), __clc_struct16_to_vector, (param0); - ld.param.v2.b32 {%r4, %r5}, [retval0]; - } // callseq 79 - st.param.v2.b32 [func_retval0], {%r4, %r5}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v2i32_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v2i32_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_1d_array_v2i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v2i32_clamp -{ - .reg .b32 %r<7>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v2i32_clamp_param_2]; - suld.b.a1d.v2.b32.clamp {%r3, %r4}, [%rd1, {%r1, %r2}]; - { // callseq 80, 0 - .param .align 4 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector2, (param0); - ld.param.v2.b32 {%r5, %r6}, [retval0]; - } // callseq 80 - st.param.v2.b32 [func_retval0], {%r5, %r6}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v2i32_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v2i32_clamp -.visible .func (.param .align 8 .b8 func_retval0[8]) __clc_llvm_nvvm_suld_2d_array_v2i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v2i32_clamp -{ - .reg .b32 %r<8>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v2i32_clamp_param_3]; - suld.b.a2d.v2.b32.clamp {%r4, %r5}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 81, 0 - .param .align 4 .b8 param0[8]; - .param .align 8 .b8 retval0[8]; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector2, (param0); - ld.param.v2.b32 {%r6, %r7}, [retval0]; - } // callseq 81 - st.param.v2.b32 [func_retval0], {%r6, %r7}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_1d_array_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_1d_array_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_1d_array_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_2 -) // @__clc_llvm_nvvm_suld_1d_array_v4i32_clamp -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_1d_array_v4i32_clamp_param_2]; - suld.b.a1d.v4.b32.clamp {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 82, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 82 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_suld_2d_array_v4i32_clamp // -- Begin function __clc_llvm_nvvm_suld_2d_array_v4i32_clamp -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_suld_2d_array_v4i32_clamp( - .param .b64 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_0, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_1, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_2, - .param .b32 __clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_3 -) // @__clc_llvm_nvvm_suld_2d_array_v4i32_clamp -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_suld_2d_array_v4i32_clamp_param_3]; - suld.b.a2d.v4.b32.clamp {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 83, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 83 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_cube_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_cube_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_cube_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_cube_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_cube_v4f32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_cube_v4f32_f32_param_3]; - tex.cube.v4.f32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 84, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 84 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_cube_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_cube_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_cube_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_cube_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_cube_v4i32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_cube_v4i32_f32_param_3]; - tex.cube.v4.s32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 85, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 85 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_cube_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_cube_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_cube_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_cube_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_cube_v4j32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_cube_v4j32_f32_param_3]; - tex.cube.v4.u32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 86, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 86 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_f32_param_2]; - tex.a1d.v4.f32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 87, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 87 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_f32_param_3]; - tex.a2d.v4.f32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 88, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 88 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_f32_param_2]; - tex.a1d.v4.s32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 89, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 89 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_f32_param_3]; - tex.a2d.v4.s32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 90, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 90 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_f32_param_2]; - tex.a1d.v4.u32.f32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 91, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 91 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_f32_param_3]; - tex.a2d.v4.u32.f32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 92, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 92 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_1d_array_v4f32_i32_param_2]; - tex.a1d.v4.f32.s32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 93, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 93 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_unified_2d_array_v4f32_i32_param_3]; - tex.a2d.v4.f32.s32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 94, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_structf32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 94 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_1d_array_v4i32_i32_param_2]; - tex.a1d.v4.s32.s32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 95, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 95 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_unified_2d_array_v4i32_i32_param_3]; - tex.a2d.v4.s32.s32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 96, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 96 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_2 -) // @__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32 -{ - .reg .b32 %r<11>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_1d_array_v4j32_i32_param_2]; - tex.a1d.v4.u32.s32 {%r3, %r4, %r5, %r6}, [%rd1, {%r1, %r2}]; - { // callseq 97, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r6; - st.param.b32 [param0+8], %r5; - st.param.b32 [param0+4], %r4; - st.param.b32 [param0], %r3; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [retval0]; - } // callseq 97 - st.param.v4.b32 [func_retval0], {%r7, %r8, %r9, %r10}; - ret; - // -- End function -} - // .globl __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32 // -- Begin function __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32 -.visible .func (.param .align 16 .b8 func_retval0[16]) __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32( - .param .b64 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_0, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_1, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_2, - .param .b32 __clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_3 -) // @__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32 -{ - .reg .b32 %r<12>; - .reg .b64 %rd<2>; - -// %bb.0: // %entry - ld.param.b64 %rd1, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_0]; - ld.param.b32 %r1, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_1]; - ld.param.b32 %r2, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_2]; - ld.param.b32 %r3, [__clc_llvm_nvvm_tex_unified_2d_array_v4j32_i32_param_3]; - tex.a2d.v4.u32.s32 {%r4, %r5, %r6, %r7}, [%rd1, {%r1, %r2, %r3, %r3}]; - { // callseq 98, 0 - .param .align 4 .b8 param0[16]; - .param .align 16 .b8 retval0[16]; - st.param.b32 [param0+12], %r7; - st.param.b32 [param0+8], %r6; - st.param.b32 [param0+4], %r5; - st.param.b32 [param0], %r4; - call.uni (retval0), __clc_struct32_to_vector, (param0); - ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [retval0]; - } // callseq 98 - st.param.v4.b32 [func_retval0], {%r8, %r9, %r10, %r11}; - ret; - // -- End function -}