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sim65_instructions.cpp
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1873 lines (1519 loc) · 23 KB
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/*
instructions.c
Copyright 2000,2001,2003,2020 by William Sheldon Simms
This file is a part of Sim65 -- a free 6502 simulator / debugger
Sim65 is free software; you can redistribute it and/or modify it under the terms
of the GNU General Public License as published by the Free Software Foundation; either
version 3, or (at your option) any later version.
Sim65 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with Sim65;
see the file COPYING. If not, visit the Free Software Foundation website at http://www.fsf.org
*/
#include <stdint.h>
#include "instructions.h"
#include "tables.h"
#ifdef OPENAPPLE
#include "apple_cpu.h"
#include "iie_memory.h"
#else
#include "AddressPeripheral.h"
#endif
/* 65c02 registers */
uint8_t A; /* Accumulator */
uint8_t X, Y; /* Index Registers */
uint8_t P = 0x34; /* Status Byte */
uint8_t S; /* Stack Pointer */
uint8_t C = 0, Z = 0, I = 1, D = 0, B = 1, V = 0, N = 0;
uint8_t interrupt_flags = 0;
uint16_t emPC;
uint64_t cycle_clock = 0;
/* Abbreviations */
/* Macros to push bytes to and pull bytes from the 65c02 stack */
#define PUSH(b) (WRITE_STACK(S,(b)),--S)
#define PULL() (++S,READ_STACK(S))
/* Addressing mode macros */
#define ABS(effaddr,index) do { \
uint16_t baseaddr; \
baseaddr = ((uint16_t)READ(emPC)); \
emPC++; \
baseaddr += (((uint16_t)READ(emPC)) << 8); \
emPC++; \
(effaddr) = baseaddr; \
if (index) { \
(effaddr) += (uint16_t)(index); \
if ((effaddr & 0xFF00) != ((baseaddr) & 0xFF00)) \
cycle_clock++; \
} \
} while(0)
#define ABS_INDIRECT(effaddr,index) do { \
uint16_t baseaddr; \
ABS(baseaddr,index); \
(effaddr) = ((uint16_t)READ(baseaddr)); \
(effaddr) += (((uint16_t)READ(baseaddr+1)) << 8); \
} while (0)
#define ZP(effaddr,index) do { \
(effaddr) = (uint16_t)(uint8_t)(READ(emPC) + (uint8_t)(index)); \
emPC++; \
} while (0)
#define ZP_INDIRECT(effaddr,index) do { \
uint8_t zpaddr; \
zpaddr = READ(emPC) + (uint8_t)(index); \
emPC++; \
(effaddr) = ((uint16_t)READ((uint16_t)zpaddr)); \
(effaddr) += (((uint16_t)READ((uint16_t)(zpaddr+1))) << 8); \
} while (0)
/* Macro to set N and Z flags */
#define SET_FLAGS_NZ(a) \
N = ((a) & 0x80) ? 1 : 0; \
Z = (a) ? 0 : 1; \
/* 65c02 addressing modes */
static unsigned short imm (void)
{
return emPC++;
}
static inline uint16_t zp_indirect (void)
{
uint16_t effaddr;
ZP_INDIRECT(effaddr,0);
return effaddr;
}
static inline uint16_t indirect_x (void)
{
uint16_t effaddr;
ZP_INDIRECT(effaddr,X);
return effaddr;
}
static inline uint16_t indirect_y (void)
{
uint16_t baseaddr;
uint16_t effaddr;
ZP_INDIRECT(baseaddr,0);
effaddr = baseaddr + (unsigned short)Y;
if ((effaddr & 0xFF00) != (baseaddr & 0xFF00))
cycle_clock++;
return effaddr;
}
static inline uint16_t absolute (void)
{
uint16_t effaddr;
ABS(effaddr,0);
return effaddr;
}
static inline uint16_t absolute_x (void)
{
uint16_t effaddr;
ABS(effaddr,X);
return effaddr;
}
static inline uint16_t absolute_y (void)
{
uint16_t effaddr;
ABS(effaddr,Y);
return effaddr;
}
static inline uint16_t zp (void)
{
uint16_t effaddr;
ZP(effaddr,0);
return effaddr;
}
static inline uint16_t zp_x (void)
{
uint16_t effaddr;
ZP(effaddr,X);
return effaddr;
}
static inline uint16_t zp_y (void)
{
uint16_t effaddr;
ZP(effaddr,Y);
return effaddr;
}
/* 65c02 relative branch */
static inline void branch (void)
{
uint16_t offset, target;
offset = (uint16_t)((int16_t)((int8_t)READ(emPC)));
emPC++;
target = emPC + offset;
++cycle_clock;
if ((emPC & 0xFF00) != (target & 0xFF00))
++cycle_clock;
emPC = target;
}
static inline void branch_bit_reset (char bit)
{
unsigned char zp_byte;
unsigned char zp_addr;
zp_addr = zp();
zp_byte = READ(zp_addr);
if (zp_byte & bit)
++emPC;
else
branch();
}
static inline void branch_bit_set (char bit)
{
unsigned char zp_byte;
unsigned char zp_addr;
zp_addr = zp();
zp_byte = READ(zp_addr);
if (zp_byte & bit)
branch();
else
++emPC;
}
static inline void reset_memory_bit (char bit)
{
unsigned char zp_byte;
unsigned char zp_addr;
zp_addr = zp();
zp_byte = READ(zp_addr);
zp_byte &= ~bit;
WRITE(zp_addr, zp_byte);
}
static inline void set_memory_bit (char bit)
{
unsigned char zp_byte;
unsigned char zp_addr;
zp_addr = zp();
zp_byte = READ(zp_addr);
zp_byte |= bit;
WRITE(zp_addr, zp_byte);
}
/* 65c02 loads */
#define LOAD(reg,addr) \
do { \
uint16_t taddr = (addr); \
(reg) = READ(taddr); \
SET_FLAGS_NZ((reg)); \
} while (0)
// stores use memory.h WRITE() macro directly
/* 65c02 ALU operations */
static inline void BIT (uint16_t addr)
{
uint8_t byte = READ(addr);
V = (byte & 0x40) ? 1 : 0;
N = (byte & 0x80) ? 1 : 0;
Z = (byte & A) ? 0 : 1;
}
static inline void ORA (uint16_t addr)
{
A |= READ(addr);
SET_FLAGS_NZ(A);
}
static inline void EOR (uint16_t addr)
{
A ^= READ(addr);
SET_FLAGS_NZ(A);
}
static inline void AND (uint16_t addr)
{
A &= READ(addr);
SET_FLAGS_NZ(A);
}
static inline void ASL (uint16_t addr)
{
uint8_t byte = READ(addr);
C = (byte & 0x80) ? 1 : 0;
byte <<= 1;
SET_FLAGS_NZ(byte);
WRITE(addr, byte);
}
static inline void LSR (uint16_t addr)
{
uint8_t byte = READ(addr);
C = byte & 0x01;
byte >>= 1;
N = 0;
Z = byte ? 0 : 1;
WRITE(addr, byte);
}
static inline void ROL (uint16_t addr)
{
uint8_t byte = READ(addr);
uint8_t result = (byte << 1) | C;
C = (byte & 0x80) ? 1 : 0;
SET_FLAGS_NZ(result);
WRITE(addr, result);
}
static inline void ROR (uint16_t addr)
{
uint8_t byte = READ(addr);
uint8_t result = byte >> 1;
result |= (C ? 0x80 : 0x00);
C = byte & 0x01;
SET_FLAGS_NZ(result);
WRITE(addr, result);
}
static inline void CMP (uint8_t regval, uint16_t addr)
{
uint8_t byte = READ(addr);
C = (regval >= byte) ? 1 : 0;
uint8_t result = regval - byte;
SET_FLAGS_NZ(result);
}
static inline void INC (uint16_t addr)
{
uint8_t byte = READ(addr) + 1;
SET_FLAGS_NZ(byte);
WRITE(addr, byte);
}
static inline void DEC (uint16_t addr)
{
uint8_t byte = READ(addr) - 1;
SET_FLAGS_NZ(byte);
WRITE(addr, byte);
}
static inline void ADC_decimal (uint16_t addr)
{
uint8_t ones, tens;
uint8_t byte = READ(addr);
/* add 'ones' digits */
ones = (A & 0xF) + (byte & 0xF) + C;
/* carry if needed */
C = 0;
if (ones >= 10)
{
C = 1;
ones -= 10;
}
/* add 'tens' digits */
tens = (A >> 4) + (byte >> 4) + C;
/* carry if needed */
C = 0;
if (tens > 9)
{
C = 1;
tens -= 10;
}
A = (tens << 4) + ones;
/* set flags */
V = C;
SET_FLAGS_NZ(A);
/* takes one cycle more than binary */
++cycle_clock;
}
static inline void SBC_decimal (uint16_t addr)
{
uint8_t ones, tens;
uint8_t byte = READ(addr);
/* subtract 'ones' digits */
ones = (A & 0xF) - (byte & 0xF) - (1 - C);
/* borrow if needed */
C = 1;
if (ones & 0x80)
{
C = 0;
ones -= 6;
}
/* subtract 'tens' digits */
tens = (A >> 4) - (byte >> 4) - (1 - C);
/* borrow if needed */
C = 1;
if (tens & 0x80)
{
C = 0;
tens -= 6;
}
A = (tens << 4) + (ones & 0xF);
/* set flags */
V = C;
SET_FLAGS_NZ(A);
/* takes one cycle more than binary */
++cycle_clock;
}
static inline void ADC_binary (uint16_t addr)
{
uint8_t high;
uint8_t byte = READ(addr);
high = A >> 7;
A = A + byte + C;
if (A & 0x80) /* A < 0 */
{
Z = 0;
N = 1;
if (byte & 0x80) /* byte < 0 */
{
C = high;
V = 0;
}
else /* byte >= 0 */
{
C = 0;
V = 1 ^ high;
}
}
else /* A >= 0 */
{
N = 0;
Z = A ? 0 : 1;
if (byte & 0x80) /* byte < 0 */
{
C = 1;
V = high;
}
else /* byte >= 0 */
{
C = high;
V = 0;
}
}
}
static inline void SBC_binary (uint16_t addr)
{
uint8_t high;
uint8_t byte = READ(addr);
high = A >> 7;
A = A - byte - (1 - C);
if (A & 0x80) /* A < 0 */
{
Z = 0;
N = 1;
if (byte & 0x80) /* byte < 0 */
{
C = 0;
V = 1 ^ high;
}
else /* byte >= 0 */
{
C = high;
V = 0;
}
}
else /* A >= 0 */
{
N = 0;
Z = A ? 0 : 1;
if (byte & 0x80) /* byte < 0 */
{
C = high;
V = 0;
}
else /* byte >= 0 */
{
C = 1;
V = high;
}
}
}
/* Convert individual bits to P and reverse */
uint8_t build_P (void)
{
P = 0x20;
if (N) P |= 0x80;
if (V) P |= 0x40;
if (B) P |= 0x10;
if (D) P |= 0x08;
if (I) P |= 0x04;
if (Z) P |= 0x02;
if (C) P |= 0x01;
return P;
}
void unbuild_P (uint8_t status)
{
P = status;
N = (P & 0x80) ? 1 : 0;
V = (P & 0x40) ? 1 : 0;
if (B == 0)
B = (P & 0x10) ? 1 : 0;
D = (P & 0x08) ? 1 : 0;
I = (P & 0x04) ? 1 : 0;
Z = (P & 0x02) ? 1 : 0;
C = (P & 0x01) ? 1 : 0;
if (D)
instruction_table = decimal_instruction_table;
else
instruction_table = binary_instruction_table;
}
/* Generate an interrupt */
void interrupt (uint16_t vector, uint8_t flag)
{
uint8_t byte;
interrupt_flags &= (~flag);
if (flag == F_RESET)
{
B = 1; /* is this for real? */
}
else
{
byte = emPC >> 8;
PUSH(byte);
byte = emPC & 0xFF;
PUSH(byte);
B = 0;
byte = build_P();
PUSH(byte);
}
I = 1;
D = 0;
instruction_table = binary_instruction_table;
build_P();
emPC = READ(vector);
vector++;
emPC = emPC + (READ(vector) << 8);
cycle_clock += 7;
}
/* 65c02 instructions */
void i00_BRK (void)
{
++emPC;
PUSH(emPC / 256);
PUSH(emPC & 255);
B = 1;
PUSH(build_P());
I = 1;
D = 0;
instruction_table = binary_instruction_table;
emPC = READ(0xfffe) + (256 * READ(0xffff));
}
void i01_ORA (void)
{
ORA(indirect_x());
}
void i02_NOP (void)
{
/* Two-Byte NOP */
emPC++;
}
void i04_TSB (void)
{
unsigned char zp_byte;
unsigned char zp_addr;
zp_addr = zp();
zp_byte = READ(zp_addr);
Z = (A & zp_byte) ? 0 : 1;
zp_byte |= A;
WRITE(zp_addr, zp_byte);
}
void i05_ORA (void)
{
ORA(zp());
}
void i06_ASL (void)
{
ASL(zp());
}
void i07_RMB (void)
{
reset_memory_bit(0x01);
}
void i08_PHP (void)
{
PUSH(build_P());
}
void i09_ORA (void)
{
ORA(imm());
}
void i0A_ASL (void)
{
C = (A & 0x80) ? 1 : 0;
A <<= 1;
SET_FLAGS_NZ(A);
}
void i0C_TSB (void)
{
unsigned char op_byte;
unsigned short op_addr;
op_addr = absolute();
op_byte = READ(op_addr);
Z = (A & op_byte) ? 0 : 1;
op_byte |= A;
WRITE(op_addr, op_byte);
}
void i0D_ORA (void)
{
ORA(absolute());
}
void i0E_ASL (void)
{
ASL(absolute());
}
void i0F_BBR (void)
{
branch_bit_reset(0x01);
}
void i10_BPL (void)
{
if (N)
++emPC;
else
branch();
}
void i11_ORA (void)
{
ORA(indirect_y());
}
void i12_ORA (void)
{
ORA(zp_indirect());
}
void i14_TRB (void)
{
unsigned char zp_addr;
unsigned char zp_byte;
zp_addr = zp();
zp_byte = READ(zp_addr);
Z = (A & zp_byte) ? 0 : 1;
zp_byte &= (~A);
WRITE(zp_addr, zp_byte);
}
void i15_ORA (void)
{
ORA(zp_x());
}
void i16_ASL (void)
{
ASL(zp_x());
}
void i17_RMB (void)
{
reset_memory_bit(0x02);
}
void i18_CLC (void)
{
C = 0;
}
void i19_ORA (void)
{
ORA(absolute_y());
}
void i1A_INC (void)
{
++A;
SET_FLAGS_NZ(A);
}
void i1C_TRB (void)
{
unsigned char op_byte;
unsigned short op_addr;
op_addr = absolute();
op_byte = READ(op_addr);
Z = (A & op_byte) ? 0 : 1;
op_byte &= (~A);
WRITE(op_addr, op_byte);
}
void i1D_ORA (void)
{
ORA(absolute_x());
}
void i1E_ASL (void)
{
ASL(absolute_x());
}
void i1F_BBR (void)
{
branch_bit_reset(0x02);
}
void i20_JSR (void)
{
unsigned short addr;
addr = emPC + 1;
PUSH(addr / 256);
PUSH(addr & 255);
emPC = absolute();
}
void i21_AND (void)
{
AND(indirect_x());
}
void i24_BIT (void)
{
BIT(zp());
}
void i25_AND (void)
{
AND(zp());
}
void i26_ROL (void)
{
ROL(zp());
}
void i27_RMB (void)
{
reset_memory_bit(0x04);
}
void i28_PLP (void)
{
unbuild_P(PULL());
}
void i29_AND (void)
{
AND(imm());
}
void i2A_ROL (void)
{
unsigned char result;
result = (A << 1) | C;
C = (A & 0x80) ? 1 : 0;
A = result;
SET_FLAGS_NZ(A);
}
void i2C_BIT (void)
{
BIT(absolute());
}
void i2D_AND (void)
{
AND(absolute());
}
void i2E_ROL (void)
{
ROL(absolute());
}
void i2F_BBR (void)
{
branch_bit_reset(0x04);
}
void i30_BMI (void)
{
if (N)
branch();
else
++emPC;
}
void i31_AND (void)
{
AND(indirect_y());
}
void i32_AND (void)
{
AND(zp_indirect());
}
void i34_BIT (void)
{
BIT(zp_x());
}
void i35_AND (void)
{
AND(zp_x());
}
void i36_ROL (void)
{
ROL(zp_x());
}
void i37_RMB (void)
{
reset_memory_bit(0x08);
}
void i38_SEC (void)
{
C = 1;
}
void i39_AND (void)
{
AND(absolute_y());
}
void i3A_DEC (void)
{
--A;
SET_FLAGS_NZ(A);
}
void i3C_BIT (void)
{
BIT(absolute_x());
}
void i3D_AND (void)
{
AND(absolute_x());
}
void i3E_ROL (void)
{
ROL(absolute_x());
}
void i3F_BBR (void)
{
branch_bit_reset(0x08);
}
void i40_RTI (void)
{
unbuild_P(PULL());
emPC = PULL();
emPC += (256 * PULL());
}
void i41_EOR (void)
{
EOR(indirect_x());
}
void i45_EOR (void)
{
EOR(zp());
}
void i46_LSR (void)
{
LSR(zp());
}
void i47_RMB (void)
{
reset_memory_bit(0x10);
}
void i48_PHA (void)
{
PUSH(A);
}
void i49_EOR (void)
{
EOR(imm());
}
void i4A_LSR (void)
{
C = A & 0x01;
A >>= 1;
N = 0;
Z = A ? 0 : 1;
}
void i4C_JMP (void)
{
emPC = absolute();
}
void i4D_EOR (void)
{
EOR(absolute());
}
void i4E_LSR (void)
{
LSR(absolute());
}
void i4F_BBR (void)
{
branch_bit_reset(0x10);
}
void i50_BVC (void)
{
if (V)
++emPC;
else
branch();
}
void i51_EOR (void)
{
EOR(indirect_y());
}
void i52_EOR (void)
{
EOR(zp_indirect());
}
void i55_EOR (void)
{
EOR(zp_x());
}
void i56_LSR (void)
{
LSR(zp_x());
}
void i57_RMB (void)
{