CHANGELOG.md

Changelog

All notable changes to this project will be documented in this file. Only releases published to PyPI are tracked here. No release candidates!

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

[0.12] - 2025-07-28

Added

• GateGraph is an alternative PyRTL logic representation, designed to simplify analysis.

Changed

• Rewrote output_to_verilog and output_verilog_testbench. The new implementation's output should be much easier to read:
  • Single-use expressions are inlined.
  • Try mangling unusable WireVector and MemBlock names first, before assigning them entirely new names.
  • Add comments to the generated Verilog that show the un-mangled names.
• Many documentation improvements:
  • Most methods and functions now have examples.
  • Consistently use canonical top-level pyrtl.* names, rather than module-level names (pyrtl.WireVector, not pyrtl.wire.WireVector).
  • Enabled intersphinx for clickable standard library references (list, dict, etc).
  • Set up doctest for examples, to verify that documentation examples still work.
• Switched from pylint and pycodestyle to ruff:
  • Applied many ruff fixes.
  • Reformatted the code with ruff format.
  • Updated tox to run ruff check and ruff format.

Removed

• Removed remaining Python 2 support.

Fixed

• Fixed XOR implementation in and_inverter_synth pass (@EdwinChang24)
• output_verilog_testbench should not re-initialize RomBlocks.
• FastSimulation was not setting init_memvalue correctly (renamed to SimulationTrace.memory_value_map).
• Specify bitwidths for Verilog initial register and memory values. They were previously unsized constants, which are implicitly 32-bit signed, which could cause surprises.

[0.11.3] - 2025-06-12

Added

• An optimization pass to optimize inverter chains (@gaborszita)
• one_hot_to_binary encoder (documentation) (@vaaniarora)
• binary_to_one_hot decoder (documentation) (@vaaniarora)

Changed

• More support for signed integers: Signed integers can now be used in RomBlock's romdata, Simulation's mem_value_map
  • And Verilog-style register reset values (@PrajwalVandana)
• Improved documentation:
  • conditional_assignment
  • WireVector equality

Fixed

• Use iteration instead of recursion to avoid stack overflow in find_producer (@gaborszita)

[0.11.2] - 2024-07-16

Added

• Added an initialize_registers option to output_to_verilog (documentation)

Changed

• Improved handling of signed integers.

Fixed

• Fixed a wire_matrix bug involving single-element matrices of Inputs or Registers.

[0.11.1] - 2024-04-22

Added

• Named WireVector slices with wire_struct and wire_matrix. See documentation:
  • wire_struct
  • wire_matrix

Changed

• Major changes to render_trace visualization. See examples and documentation
• Many documentation and release process improvements.

Fixed

• Python 3.11 compatibility.

Removed

• Python 2.7 support.