neuron_tb

#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "F:\iverilog\lib\ivl\system.vpi";
:vpi_module "F:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "F:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "F:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "F:\iverilog\lib\ivl\va_math.vpi";
:vpi_module "F:\iverilog\lib\ivl\v2009.vpi";
S_0000018457754db0 .scope package, "$unit" "$unit" 2 1;
 .timescale 0 0;
S_000001845775a1c0 .scope module, "neuron_tb" "neuron_tb" 3 3;
 .timescale -12 -12;
v00000184577cd620_0 .var/s "b", 7 0;
v00000184577ceac0_0 .var "clk", 0 0;
v00000184577cd3a0_0 .var "rst_n", 0 0;
v00000184577cec00_0 .var/i "test_nums", 31 0;
v00000184577ce660_0 .var/i "total_tests", 31 0;
v00000184577ce520_0 .var/s "w", 7 0;
v00000184577ce5c0_0 .var/s "x", 7 0;
v00000184577cd1c0_0 .net/s "y", 17 0, L_000001845776e040;  1 drivers
S_000001845775a350 .scope module, "dut" "neuron" 3 17, 4 1 0, S_000001845775a1c0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 8 "x";
    .port_info 3 /INPUT 8 "w";
    .port_info 4 /INPUT 8 "bias";
    .port_info 5 /OUTPUT 18 "y";
L_000001845776e040 .functor BUFZ 18, v00000184577ce0c0_0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>;
v00000184577789d0_0 .net/s "accumulated", 16 0, L_000001845776dcc0;  1 drivers
v0000018457778a70_0 .var/s "accumulated_reg", 16 0;
v0000018457777b70_0 .net/s "activated_output", 17 0, L_000001845776e430;  1 drivers
v00000184577ce0c0_0 .var/s "activated_output_reg", 17 0;
v00000184577cdda0_0 .net/s "bias", 7 0, v00000184577cd620_0;  1 drivers
v00000184577cde40_0 .net "clk", 0 0, v00000184577ceac0_0;  1 drivers
v00000184577cd6c0_0 .net/s "partial_output", 17 0, L_000001845776e350;  1 drivers
v00000184577ce160_0 .var/s "partial_output_reg", 17 0;
v00000184577cdee0_0 .net "rst_n", 0 0, v00000184577cd3a0_0;  1 drivers
v00000184577ce3e0_0 .net/s "w", 7 0, v00000184577ce520_0;  1 drivers
v00000184577cd440_0 .var/s "w_reg", 7 0;
v00000184577cdf80_0 .net/s "x", 7 0, v00000184577ce5c0_0;  1 drivers
v00000184577ce340_0 .var/s "x_reg", 7 0;
v00000184577cdb20_0 .net/s "y", 17 0, L_000001845776e040;  alias, 1 drivers
S_000001845776f430 .scope module, "act_u" "activate" 4 66, 5 27 0, S_000001845775a350;
 .timescale -12 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 18 "in";
    .port_info 3 /OUTPUT 18 "out";
L_000001845776e430 .functor BUFZ 18, v0000018457777df0_0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>;
v0000018457777d50_0 .net "clk", 0 0, v00000184577ceac0_0;  alias, 1 drivers
v0000018457778890_0 .net/s "in", 17 0, v00000184577ce160_0;  1 drivers
v0000018457778390_0 .net/s "out", 17 0, L_000001845776e430;  alias, 1 drivers
v0000018457778570_0 .net "rst_n", 0 0, v00000184577cd3a0_0;  alias, 1 drivers
v0000018457777df0_0 .var/s "temp", 17 0;
E_00000184577484f0 .event posedge, v0000018457777d50_0;
S_000001845776f5c0 .scope module, "add_u" "adder" 4 48, 6 2 0, S_000001845775a350;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 17 "in1";
    .port_info 3 /INPUT 8 "in2";
    .port_info 4 /OUTPUT 17 "sum";
    .port_info 5 /OUTPUT 1 "carry";
    .port_info 6 /OUTPUT 18 "total";
L_000001845776e350 .functor BUFZ 18, v0000018457778110_0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>;
v0000018457777f30_0 .net *"_ivl_1", 0 0, L_00000184577cd4e0;  1 drivers
v0000018457777cb0_0 .net *"_ivl_2", 8 0, L_00000184577cd800;  1 drivers
v0000018457778610_0 .net "carry", 0 0, L_00000184577ce700;  1 drivers
v0000018457778250_0 .net "clk", 0 0, v00000184577ceac0_0;  alias, 1 drivers
v0000018457778930_0 .net/s "in1", 16 0, v0000018457778a70_0;  1 drivers
v0000018457778430_0 .net/s "in2", 7 0, v00000184577cd620_0;  alias, 1 drivers
v0000018457777fd0_0 .net "rst_n", 0 0, v00000184577cd3a0_0;  alias, 1 drivers
v00000184577784d0_0 .net/s "sign_ext", 16 0, L_00000184577cdbc0;  1 drivers
v00000184577782f0_0 .net/s "sum", 16 0, L_00000184577ce020;  1 drivers
v0000018457778110_0 .var/s "temp", 17 0;
v0000018457778750_0 .net/s "total", 17 0, L_000001845776e350;  alias, 1 drivers
E_0000018457748530/0 .event negedge, v0000018457778570_0;
E_0000018457748530/1 .event posedge, v0000018457777d50_0;
E_0000018457748530 .event/or E_0000018457748530/0, E_0000018457748530/1;
L_00000184577cd4e0 .part v00000184577cd620_0, 7, 1;
LS_00000184577cd800_0_0 .concat [ 1 1 1 1], L_00000184577cd4e0, L_00000184577cd4e0, L_00000184577cd4e0, L_00000184577cd4e0;
LS_00000184577cd800_0_4 .concat [ 1 1 1 1], L_00000184577cd4e0, L_00000184577cd4e0, L_00000184577cd4e0, L_00000184577cd4e0;
LS_00000184577cd800_0_8 .concat [ 1 0 0 0], L_00000184577cd4e0;
L_00000184577cd800 .concat [ 4 4 1 0], LS_00000184577cd800_0_0, LS_00000184577cd800_0_4, LS_00000184577cd800_0_8;
L_00000184577cdbc0 .concat [ 8 9 0 0], v00000184577cd620_0, L_00000184577cd800;
L_00000184577ce020 .part v0000018457778110_0, 0, 17;
L_00000184577ce700 .part v0000018457778110_0, 17, 1;
S_0000018457769a00 .scope module, "mac_u" "mac" 4 32, 7 2 0, S_000001845775a350;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 8 "x";
    .port_info 3 /INPUT 8 "weight";
    .port_info 4 /OUTPUT 17 "out";
L_000001845776dcc0 .functor BUFZ 17, v0000018457777e90_0, C4<00000000000000000>, C4<00000000000000000>, C4<00000000000000000>;
v0000018457777e90_0 .var/s "accumulator", 16 0;
v0000018457778070_0 .net "clk", 0 0, v00000184577ceac0_0;  alias, 1 drivers
v00000184577781b0_0 .net/s "out", 16 0, L_000001845776dcc0;  alias, 1 drivers
v00000184577786b0_0 .net "rst_n", 0 0, v00000184577cd3a0_0;  alias, 1 drivers
v00000184577787f0_0 .net/s "weight", 7 0, v00000184577cd440_0;  1 drivers
v0000018457777c10_0 .net/s "x", 7 0, v00000184577ce340_0;  1 drivers
S_0000018457769b90 .scope task, "test" "test" 3 29, 3 29 0, S_000001845775a1c0;
 .timescale -12 -12;
v00000184577cd9e0_0 .var/s "a", 7 0;
v00000184577cea20_0 .var/s "accumulate", 16 0;
v00000184577ced40_0 .var/s "activate", 17 0;
v00000184577ce200_0 .var/s "bias", 7 0;
v00000184577ce2a0_0 .var/s "bias_ext", 16 0;
v00000184577ce480_0 .var/s "expected", 17 0;
v00000184577cd260_0 .var/s "out", 17 0;
v00000184577cd120_0 .var/s "product", 15 0;
v00000184577ce8e0_0 .var/s "product_ext", 16 0;
v00000184577cd760_0 .var/s "weight", 7 0;
TD_neuron_tb.test ;
    %pushi/vec4 0, 0, 17;
    %store/vec4 v00000184577cea20_0, 0, 17;
    ; show_stmt_assign_vector: Get l-value for compressed += operand
    %load/vec4 v00000184577ce660_0;
    %pushi/vec4 1, 0, 32;
    %add;
    %store/vec4 v00000184577ce660_0, 0, 32;
    ; show_stmt_assign_vector: Get l-value for compressed += operand
    %load/vec4 v00000184577cec00_0;
    %pushi/vec4 1, 0, 32;
    %add;
    %store/vec4 v00000184577cec00_0, 0, 32;
    %load/vec4 v00000184577cd9e0_0;
    %store/vec4 v00000184577ce5c0_0, 0, 8;
    %load/vec4 v00000184577cd760_0;
    %store/vec4 v00000184577ce520_0, 0, 8;
    %load/vec4 v00000184577ce200_0;
    %store/vec4 v00000184577cd620_0, 0, 8;
    %load/vec4 v00000184577cd9e0_0;
    %pad/s 16;
    %load/vec4 v00000184577ce520_0;
    %pad/s 16;
    %mul;
    %store/vec4 v00000184577cd120_0, 0, 16;
    %load/vec4 v00000184577cd120_0;
    %parti/s 1, 15, 5;
    %load/vec4 v00000184577cd120_0;
    %concat/vec4; draw_concat_vec4
    %store/vec4 v00000184577ce8e0_0, 0, 17;
    %load/vec4 v00000184577ce8e0_0;
    %load/vec4 v00000184577cea20_0;
    %add;
    %store/vec4 v00000184577cea20_0, 0, 17;
    %delay 1, 0;
    %load/vec4 v00000184577ce200_0;
    %parti/s 1, 7, 4;
    %replicate 9;
    %load/vec4 v00000184577ce200_0;
    %concat/vec4; draw_concat_vec4
    %store/vec4 v00000184577ce2a0_0, 0, 17;
    %load/vec4 v00000184577cea20_0;
    %pad/s 18;
    %load/vec4 v00000184577ce2a0_0;
    %pad/s 18;
    %add;
    %store/vec4 v00000184577ced40_0, 0, 18;
    %delay 1, 0;
    %load/vec4 v00000184577ced40_0;
    %parti/s 1, 17, 6;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.0, 8;
    %pushi/vec4 0, 0, 18;
    %store/vec4 v00000184577cd260_0, 0, 18;
    %jmp T_0.1;
T_0.0 ;
    %load/vec4 v00000184577ced40_0;
    %store/vec4 v00000184577cd260_0, 0, 18;
T_0.1 ;
    %delay 1, 0;
    %load/vec4 v00000184577cd260_0;
    %store/vec4 v00000184577ce480_0, 0, 18;
    %delay 1, 0;
    %pushi/vec4 7, 0, 32;
T_0.2 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_0.3, 5;
    %jmp/1 T_0.3, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_00000184577484f0;
    %jmp T_0.2;
T_0.3 ;
    %pop/vec4 1;
    %delay 1, 0;
    %load/vec4 v00000184577cd1c0_0;
    %load/vec4 v00000184577ce480_0;
    %cmp/ne;
    %jmp/0xz  T_0.4, 6;
    %vpi_call/w 3 70 "$display", "Testcase Failed (%0d/%0d) \012 Expected:  %0d\012 Obtained: %0d", v00000184577cec00_0, v00000184577ce660_0, v00000184577ce480_0, v00000184577cd1c0_0 {0 0 0};
    %jmp T_0.5;
T_0.4 ;
    %vpi_call/w 3 74 "$display", "Testcase Passed (%0d/%0d) \012 Expected:  %0d\012 Obtained: %0d ", v00000184577cec00_0, v00000184577ce660_0, v00000184577ce480_0, v00000184577cd1c0_0 {0 0 0};
T_0.5 ;
    %end;
    .scope S_0000018457769a00;
T_1 ;
    %wait E_0000018457748530;
    %load/vec4 v00000184577786b0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.0, 8;
    %pushi/vec4 0, 0, 17;
    %assign/vec4 v0000018457777e90_0, 0;
    %jmp T_1.1;
T_1.0 ;
    %load/vec4 v0000018457777c10_0;
    %pad/s 17;
    %load/vec4 v00000184577787f0_0;
    %pad/s 17;
    %mul;
    %load/vec4 v0000018457777e90_0;
    %add;
    %assign/vec4 v0000018457777e90_0, 0;
T_1.1 ;
    %jmp T_1;
    .thread T_1;
    .scope S_000001845776f5c0;
T_2 ;
    %wait E_0000018457748530;
    %load/vec4 v0000018457777fd0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.0, 8;
    %pushi/vec4 0, 0, 18;
    %assign/vec4 v0000018457778110_0, 0;
    %jmp T_2.1;
T_2.0 ;
    %load/vec4 v0000018457778930_0;
    %pad/s 18;
    %load/vec4 v00000184577784d0_0;
    %pad/s 18;
    %add;
    %assign/vec4 v0000018457778110_0, 0;
T_2.1 ;
    %jmp T_2;
    .thread T_2;
    .scope S_000001845776f430;
T_3 ;
    %wait E_00000184577484f0;
    %load/vec4 v0000018457778570_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.0, 8;
    %pushi/vec4 0, 0, 18;
    %assign/vec4 v0000018457777df0_0, 0;
    %jmp T_3.1;
T_3.0 ;
    %load/vec4 v0000018457778890_0;
    %parti/s 1, 17, 6;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.2, 8;
    %pushi/vec4 0, 0, 18;
    %assign/vec4 v0000018457777df0_0, 0;
    %jmp T_3.3;
T_3.2 ;
    %load/vec4 v0000018457778890_0;
    %assign/vec4 v0000018457777df0_0, 0;
T_3.3 ;
T_3.1 ;
    %jmp T_3;
    .thread T_3;
    .scope S_000001845775a350;
T_4 ;
    %wait E_0000018457748530;
    %load/vec4 v00000184577cdee0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.0, 8;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v00000184577ce340_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v00000184577cd440_0, 0;
    %jmp T_4.1;
T_4.0 ;
    %load/vec4 v00000184577cdf80_0;
    %assign/vec4 v00000184577ce340_0, 0;
    %load/vec4 v00000184577ce3e0_0;
    %assign/vec4 v00000184577cd440_0, 0;
T_4.1 ;
    %jmp T_4;
    .thread T_4;
    .scope S_000001845775a350;
T_5 ;
    %wait E_0000018457748530;
    %load/vec4 v00000184577cdee0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_5.0, 8;
    %pushi/vec4 0, 0, 17;
    %assign/vec4 v0000018457778a70_0, 0;
    %jmp T_5.1;
T_5.0 ;
    %load/vec4 v00000184577789d0_0;
    %assign/vec4 v0000018457778a70_0, 0;
T_5.1 ;
    %jmp T_5;
    .thread T_5;
    .scope S_000001845775a350;
T_6 ;
    %wait E_0000018457748530;
    %load/vec4 v00000184577cdee0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_6.0, 8;
    %pushi/vec4 0, 0, 18;
    %assign/vec4 v00000184577ce160_0, 0;
    %jmp T_6.1;
T_6.0 ;
    %load/vec4 v00000184577cd6c0_0;
    %assign/vec4 v00000184577ce160_0, 0;
T_6.1 ;
    %jmp T_6;
    .thread T_6;
    .scope S_000001845775a350;
T_7 ;
    %wait E_0000018457748530;
    %load/vec4 v00000184577cdee0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_7.0, 8;
    %pushi/vec4 0, 0, 18;
    %assign/vec4 v00000184577ce0c0_0, 0;
    %jmp T_7.1;
T_7.0 ;
    %load/vec4 v0000018457777b70_0;
    %assign/vec4 v00000184577ce0c0_0, 0;
T_7.1 ;
    %jmp T_7;
    .thread T_7;
    .scope S_000001845775a1c0;
T_8 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000184577ce660_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000184577cec00_0, 0, 32;
    %end;
    .thread T_8, $init;
    .scope S_000001845775a1c0;
T_9 ;
    %delay 5, 0;
    %load/vec4 v00000184577ceac0_0;
    %inv;
    %store/vec4 v00000184577ceac0_0, 0, 1;
    %jmp T_9;
    .thread T_9;
    .scope S_000001845775a1c0;
T_10 ;
    %vpi_call/w 3 81 "$dumpfile", "neuron.vcd" {0 0 0};
    %vpi_call/w 3 82 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001845775a1c0 {0 0 0};
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000184577ceac0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v00000184577ce5c0_0, 0, 8;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v00000184577ce520_0, 0, 8;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v00000184577cd620_0, 0, 8;
    %delay 10, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %pushi/vec4 3, 0, 8;
    %store/vec4 v00000184577cd9e0_0, 0, 8;
    %pushi/vec4 2, 0, 8;
    %store/vec4 v00000184577cd760_0, 0, 8;
    %pushi/vec4 1, 0, 8;
    %store/vec4 v00000184577ce200_0, 0, 8;
    %fork TD_neuron_tb.test, S_0000018457769b90;
    %join;
    %delay 1, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %delay 1, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %pushi/vec4 10, 0, 8;
    %store/vec4 v00000184577cd9e0_0, 0, 8;
    %pushi/vec4 10, 0, 8;
    %store/vec4 v00000184577cd760_0, 0, 8;
    %pushi/vec4 251, 0, 8;
    %store/vec4 v00000184577ce200_0, 0, 8;
    %fork TD_neuron_tb.test, S_0000018457769b90;
    %join;
    %delay 1, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %delay 1, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %pushi/vec4 251, 0, 8;
    %store/vec4 v00000184577cd9e0_0, 0, 8;
    %pushi/vec4 5, 0, 8;
    %store/vec4 v00000184577cd760_0, 0, 8;
    %pushi/vec4 4, 0, 8;
    %store/vec4 v00000184577ce200_0, 0, 8;
    %fork TD_neuron_tb.test, S_0000018457769b90;
    %join;
    %delay 1, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %delay 1, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %pushi/vec4 100, 0, 8;
    %store/vec4 v00000184577cd9e0_0, 0, 8;
    %pushi/vec4 1, 0, 8;
    %store/vec4 v00000184577cd760_0, 0, 8;
    %pushi/vec4 128, 0, 8;
    %store/vec4 v00000184577ce200_0, 0, 8;
    %fork TD_neuron_tb.test, S_0000018457769b90;
    %join;
    %delay 1, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %delay 1, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000184577cd3a0_0, 0, 1;
    %pushi/vec4 4, 0, 8;
    %store/vec4 v00000184577cd9e0_0, 0, 8;
    %pushi/vec4 4, 0, 8;
    %store/vec4 v00000184577cd760_0, 0, 8;
    %pushi/vec4 4, 0, 8;
    %store/vec4 v00000184577ce200_0, 0, 8;
    %fork TD_neuron_tb.test, S_0000018457769b90;
    %join;
    %vpi_call/w 3 122 "$display", "Neuron Testbench complete: %0d tests run", v00000184577ce660_0 {0 0 0};
    %vpi_call/w 3 123 "$finish" {0 0 0};
    %end;
    .thread T_10;
# The file index is used to find the file name in the following table.
:file_names 8;
    "N/A";
    "<interactive>";
    "-";
    "functional/neuron_tb.sv";
    "src/neuron.sv";
    "src/activate.sv";
    "src/adder.sv";
    "src/mac.sv";