The current control loop is written in Verilog. It works in simulation but fails when put into hardware. My bet is on failures due to the control loop math file, particularly the very large width arithmetic used.
A few solutions:
- Rewrite control_loop_math to use an ALU. This ALU only has to do addition, subtraction, multiplication.
- Rewrite control loop to be a real time module on Linux.
- Rewrite control loop to run on a coprocessor (branch)
The current control loop is written in Verilog. It works in simulation but fails when put into hardware. My bet is on failures due to the control loop math file, particularly the very large width arithmetic used.
A few solutions: